Misplaced Pages

Random-access memory: Difference between revisions

Article snapshot taken from Wikipedia with creative commons attribution-sharealike license. Give it a read and then ask your questions in the chat. We can research this topic together.
Browse history interactively← Previous editContent deleted Content addedVisualWikitext
Revision as of 10:46, 15 October 2009 view source121.6.31.12 (talk) removed duplicate section← Previous edit Latest revision as of 23:51, 16 January 2025 view source Kvng (talk | contribs)Extended confirmed users, New page reviewers108,451 edits review: hyphens. reorder for flow. 
Line 1: Line 1:
{{short description|Form of computer data storage}}
{{Redirect|RAM|other uses of the word|Ram (disambiguation)}}
{{Redirect|RAM|other uses|RAM (disambiguation)}}
{{Distinguish|Random Access Memories|Random-access machine}}
{{pp-protected|small=yes}}


] ] random-access memory: Synchronous ] ], primarily used as main memory in ], ]s, and ]s.]] ] ] random-access memory: Synchronous ] ], primarily used as main memory in ], ]s, and ]s.]]
{{Memory types}} {{Memory types}}
]]]
] RAM stick with a white ]]]


'''Random-access memory''' ('''RAM'''; {{IPAc-en|r|æ|m}}) is a form of ] that can be read and changed in any order, typically used to store working ] and ].<ref>{{cite web |title=RAM |url=https://dictionary.cambridge.org/dictionary/english/ram |website=] |access-date=11 July 2019}}</ref><ref>{{cite web |title=RAM |url=https://www.oxfordlearnersdictionaries.com/definition/american_english/ram_2 |website=] |access-date=11 July 2019}}</ref> A ] memory device allows data items to be ] or written in almost the same amount of time irrespective of the physical location of data inside the memory, in contrast with other direct-access data storage media (such as ]s and ]), where the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.
'''Random-access memory''' (usually known by its ], '''RAM''') is a form of ]. Today, it takes the form of ]s that allow stored ] to be accessed in any order (i.e., at '']''). The word ''random'' thus refers to the fact that any piece of data can be returned in a ], regardless of its physical location and whether or not it is related to the previous piece of data.<ref>''Strictly speaking, modern types of DRAM are therefore not truly (or technically) random access, as data are read in burst, although the name DRAM / RAM has stuck. However, many types of ], ], ], and ] are still ] even in a strict sense.''</ref>


In today's technology, random-access memory takes the form of ] (IC) chips with ] (metal–oxide–semiconductor) ]. RAM is normally associated with ] types of memory where stored information is lost if power is removed. The two main types of volatile random-access ] are ] (SRAM) and ] (DRAM).
By contrast, storage devices such as magnetic discs and ]s rely on the physical movement of the recording medium or a reading head. In these devices, the movement takes longer than data transfer, and the retrieval time varies based on the physical location of the next item.


Non-volatile RAM has also been developed<ref>{{cite magazine|last=Gallagher|first=Sean|title=Memory that never forgets: non-volatile DIMMs hit the market|url=https://arstechnica.com/information-technology/2013/04/memory-that-never-forgets-non-volatile-dimms-hit-the-market/|magazine=]|url-status=live|archive-url=https://web.archive.org/web/20170708073138/https://arstechnica.com/information-technology/2013/04/memory-that-never-forgets-non-volatile-dimms-hit-the-market/|archive-date=July 8, 2017|date=April 4, 2013}}</ref> and other types of ] allow random access for read operations, but either do not allow write operations or have other kinds of limitations. These include most types of ] and ].
The word RAM is often associated with ] types of memory (such as ] ]), where the information is lost after the power is switched off. Many other types of memory are RAM, too, including most types of ] and ] called '']''.

The use of semiconductor RAM dates back to 1965 when IBM introduced the monolithic (single-chip) 16-bit SP95 SRAM chip for their ] computer, and ] used bipolar DRAM memory cells for its 180-bit Toscal BC-1411 ], both based on ]s. While it offered higher speeds than ], bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.<ref>{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=Computer History Museum}}</ref> In 1966, Dr. ] invented modern DRAM architecture in which there's a single MOS transistor per capacitor.<ref>{{Cite patent|number=US3387286A|title=Field-effect transistor memory|gdate=1968-06-04|invent1=Dennard|inventor1-first=Robert H.|url=https://patents.google.com/patent/US3387286A}}</ref> The first commercial DRAM IC chip, the 1K ], was introduced in October 1970. ] (SDRAM) was reintroduced with the ] KM48SL2000 chip in 1992.


==History== ==History==
]s from the mid-1930s used ]s to store information.]]
An early type of widespread ''writable'' random-access memory was the ], developed from 1949 to 1952, and subsequently used in most computers up until the development of the static and dynamic integrated RAM circuits in the late 1960s and early 1970s. Before this, computers used ]s, ], or various kinds of ] arrangements to implement "main" memory functions (i.e., hundreds or thousands of bits); some of which were ''random access'', some not. ]es built out of vacuum tube triodes, and later, out of discrete ]s, were used for smaller and faster memories such as registers and random-access register banks. Prior to the development of integrated ROM circuits, ''permanent'' (or ''read-only'') random-access memory was often constructed using ] matrices driven by ]s.


Early computers used ]s, ]s<ref>{{cite web|url=http://www-03.ibm.com/ibm/history/reference/faq_0000000011.html|title=IBM Archives -- FAQ's for Products and Services|work=ibm.com|url-status=dead|archive-url=https://web.archive.org/web/20121023184527/http://www-03.ibm.com/ibm/history/reference/faq_0000000011.html|archive-date=2012-10-23}}</ref> or ] for main memory functions. Ultrasonic delay lines were ] which could only reproduce data in the order it was written. ] could be expanded at relatively low cost but efficient retrieval of memory items requires knowledge of the physical layout of the drum to optimize speed. Latches built out of ]s, and later, out of ]s, were used for smaller and faster memories such as ]. Such registers were relatively large and too costly to use for large amounts of data; generally only a few dozen or few hundred bits of such memory could be provided.
== Overview ==
===Types of RAM===
]] in 1989]]
Modern types of ''writable'' RAM generally store a ] in either the state of a ], as in ] (static RAM), or as a ] in a ] (or ] gate), as in ] (dynamic RAM), ], ] and ]. Some types have circuitry to detect and/or correct random faults called ''memory errors'' in the stored data, using ]s or ]. RAM of the ''read-only'' type, ], instead uses a metal mask to permanently enable/disable selected transistors, instead of storing a charge in them.


The first practical form of random-access memory was the ]. It stored data as electrically charged spots on the face of a ]. Since the electron beam of the CRT could read and write the spots on the tube in any order, memory was random access. The capacity of the Williams tube was a few hundred to around a thousand bits, but it was much smaller, faster, and more power-efficient than using individual vacuum tube latches. Developed at the ] in England, the Williams tube provided the medium on which the first electronically stored program was implemented in the ] computer, which first successfully ran a program on 21 June, 1948.<ref>{{Citation | last = Napper | first = Brian | title = Computer 50: The University of Manchester Celebrates the Birth of the Modern Computer | url = http://www.computer50.org/ | access-date = 26 May 2012 | url-status = dead | archive-url = https://web.archive.org/web/20120504133240/http://www.computer50.org/ | archive-date = 4 May 2012 }}</ref> In fact, rather than the Williams tube memory being designed for the Baby, the Baby was a ] to demonstrate the reliability of the memory.<ref>{{Citation |last1=Williams |first1=F. C. |last2=Kilburn |first2=T. |title=Electronic Digital Computers |journal=Nature |volume=162 |pages=487 |date=Sep 1948 |doi=10.1038/162487a0 |issue=4117 |postscript=. |bibcode=1948Natur.162..487W |s2cid=4110351|doi-access=free }} Reprinted in ''The Origins of Digital Computers''.</ref><ref>{{Citation |last1=Williams |first1=F. C. |last2=Kilburn |first2=T. |last3=Tootill |first3=G. C. |title=Universal High-Speed Digital Computers: A Small-Scale Experimental Machine |url=http://www.computer50.org/kgill/mark1/ssem.html |journal=Proc. IEE |date=Feb 1951 |volume=98 |issue=61 |pages=13–28 |postscript=. |doi=10.1049/pi-2.1951.0004 |url-status=dead |archive-url=https://web.archive.org/web/20131117101730/http://www.computer50.org/kgill/mark1/ssem.html |archive-date=2013-11-17}}</ref>
As both SRAM and DRAM are ''volatile'', other forms of computer storage, such as ] and ], have been used as ] in traditional computers. Many newer products instead rely on ] to maintain data when not in use, such as ]s or small music players. Certain ]s, such as many ] and ], have also replaced magnetic disks with ]s. With flash memory, only the ] is capable of true random access, allowing direct code execution, and is therefore often used instead of ROM; the lower cost ] is commonly used for bulk storage in ] and ].


] was invented in 1947 and developed up until the mid-1970s. It became a widespread form of random-access memory, relying on an array of magnetized rings. By changing the sense of each ring's magnetization, data could be stored with one bit stored per ring. Since every ring had a combination of address wires to select and read or write it, access to any memory location in any sequence was possible. Magnetic core memory was the standard form of ] until displaced by ] in ]s (ICs) during the early 1970s.<ref name="computerhistory1970"/>
Similar to a microprocessor, a memory chip is an integrated circuit (IC) made of millions of transistors and capacitors. In the most common form of computer memory, dynamic random access memory (DRAM), a transistor and a capacitor are paired to create a memory cell, which represents a single bit of data. The capacitor holds the bit of information—a 0 or a 1 . The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or change its state.


Prior to the development of integrated ] (ROM) circuits, ''permanent'' (or ''read-only'') random-access memory was often constructed using ] driven by ]s, or specially wound ] planes.{{Citation needed|date=December 2016}}
===Memory hierarchy===
Many computer systems have a memory hierarchy consisting of ]s, on-die ] caches, external ]s, ], ] systems, and ] or ] on a hard drive. This entire pool of memory may be referred to as "RAM" by many developers, even though the various subsystems can have very different ]s, violating the original concept behind the ''random access'' term in RAM. Even within a hierarchy level such as DRAM, the specific row, column, bank, rank, channel, or ] organization of the components make the access time variable, although not to the extent that rotating ] or a tape is variable. The overall goal of using a memory hierarchy is to obtain the higher possible average access performance while minimizing the total cost of entire memory system. (Generally, the memory hierarchy follows the access time with the fast CPU registers at the top and the slow hard drive at the bottom.)


] appeared in the 1960s with bipolar memory, which used ]s. Although it was faster, it could not compete with the lower price of magnetic core memory.<ref name="computerhistory1966"/>
In many modern personal computers, the RAM comes in an easily upgraded form of modules called ''']s''' or '''DRAM modules''' about the size of a few sticks of chewing gum. These can quickly be replaced should they become damaged or too small for current purposes. As suggested above, ''smaller'' amounts of RAM (mostly SRAM) are also integrated in the ] and other ]s on the ], as well as in hard-drives, ]s, and several other parts of the computer system.


====Swapping==== ===MOS RAM===
In 1957, Frosch and Derick manufactured the first silicon dioxide field-effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface.<ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650}}</ref> Subsequently, in 1960, a team demonstrated a working ] at Bell Labs.<ref>{{Cite journal |last=KAHNG |first=D. |date=1961 |title=Silicon-Silicon Dioxide Surface Device |url=https://doi.org/10.1142/9789814503464_0076 |journal=Technical Memorandum of Bell Laboratories |pages=583–596 |doi=10.1142/9789814503464_0076 |isbn=978-981-02-0209-5}}</ref><ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref> This led to the development of ] (MOS) memory by John Schmidt at ] in 1964.<ref name="computerhistory1970" /><ref>{{Cite book |url=https://books.google.com/books?id=kG4rAQAAIAAJ&q=John+Schmidt |title=Solid State Design – Vol. 6 |date=1965 |publisher=Horizon House}}</ref> In addition to higher speeds, MOS ] was cheaper and consumed less power than magnetic core memory.<ref name="computerhistory1970" /> The development of ] ] (MOS IC) technology by ] at Fairchild in 1968 enabled the production of MOS ]s.<ref>{{cite web |title=1968: Silicon Gate Technology Developed for ICs |url=https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ |website=] |access-date=10 August 2019}}</ref> MOS memory overtook magnetic core memory as the dominant memory technology in the early 1970s.<ref name="computerhistory1970" />
If a computer becomes low on RAM during intensive application cycles, many CPU architectures and operating systems are able to perform an operation known as "]". Swapping uses a ''paging file'', an area on a ] temporarily used as additional working memory. Constant use of this mechanism is called ] and is generally undesirable because it lowers overall system performance, mainly because hard drives are slower than RAM.


Integrated bipolar ] (SRAM) was invented by Robert H. Norman at ] in 1963.<ref>{{cite patent
On some operating systems (such as ]) it is possible to turn swapping off such that no memory is written to the hard disk ("swapoff -a" as superuser on startup). This can reduce latency as well as hard disk wear, but if one does not have enough RAM then the OS will freeze and perhaps ]. {{Citation needed|date August 2009|date=July 2009}}
| country = US
| number = 3562721
| status = patent
| title = Solid State Switching and Memory Apparatus
| pubdate = 9 February 1971
| fdate = 5 March 1963
| pridate = 5 March 1963
| inventor = Robert H. Norman
| invent1 = Fairchild Camera and Instrument Corporation
}}</ref> It was followed by the development of MOS SRAM by John Schmidt at Fairchild in 1964.<ref name="computerhistory1970"/> SRAM became an alternative to magnetic-core memory, but required six MOS transistors for each ] of data.<ref name="ibm100">{{cite web |title=DRAM |url=https://www.ibm.com/ibm/history/ibm100/us/en/icons/dram/ |website=IBM100 |publisher=] |access-date=20 September 2019 |date=9 August 2017}}</ref> Commercial use of SRAM began in 1965, when ] introduced the SP95 memory chip for the ].<ref name="computerhistory1966"/>


] (DRAM) allowed replacement of a 4 or 6-transistor latch circuit by a single transistor for each memory bit, greatly increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor and had to be periodically ] every few milliseconds before the charge could leak away.
===Other uses of the "RAM" term===
Other physical devices with read–write capability can have "RAM" in their names: for example, ]. "Random access" is also the name of an indexing method: hence, disk storage is often called "random access"( ], ], ], ], ] ) because the reading head can move relatively quickly from one piece of data to another, and does not have to read all the data in between. However the final "M" is crucial: "RAM" (provided there is no additional term as in "DVD-RAM") always refers to a solid-state device.


]'s Toscal BC-1411 ], which was introduced in 1965,<ref>. {{webarchive|url=https://web.archive.org/web/20170729145228/http://collection.sciencemuseum.org.uk/objects/co8406093/toscal-bc-1411-calculator-with-electronic-calculator |date=2017-07-29 }}, ].</ref><ref name="bc-spec" /><ref name="bc" /> used a form of capacitor bipolar DRAM, storing 180-bit data on discrete ], consisting of ] bipolar transistors and capacitors.<ref name="bc-spec" /><ref name="bc" /> Capacitors had also been used for earlier memory schemes, such as the drum of the ], the ] and the ]. While it offered higher speeds than magnetic-core memory, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.<ref>{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=Computer History Museum}}</ref><!--]-->
Often, RAM is a shorthand in on-line conversations for referring to the computer's main working memory.


] (Mbit) DRAM chip, one of the last models developed by ], in 1989]]
====RAM disks====
In 1966, ] invented modern DRAM architecture for which there is a single MOS transistor per capacitor.<ref name="ibm100" /> While examining the characteristics of MOS technology, he found it was capable of building ]s, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell.<ref name="ibm100"/> In 1967, Dennard filed a patent under IBM for a single-transistor DRAM memory cell, based on MOS technology.<ref name="Robert Dennard"/> The first commercial DRAM IC chip was the ], which was ] on an ] MOS process with a capacity of 1{{nbsp}}], and was released in 1970.<ref name="computerhistory1970"/><ref name="Lojek-1103"/><ref>{{cite web |first=Mary |last=Bellis |url=http://inventors.about.com/library/weekly/aa100898.htm |title=The Invention of the Intel 1103 |access-date=2015-07-11 |archive-date=2020-03-14 |archive-url=https://web.archive.org/web/20200314061801/http://inventors.about.com/library/weekly/aa100898.htm |url-status=dead }}</ref>
Software can "partition" a portion of a computer's RAM, allowing it to act as a much faster hard drive that is called a ]. Unless the memory used is non-volatile, a RAM disk loses the stored data when the computer is shut down. However, volatile memory can retain its data when the computer is shut down if it has a separate power source, usually a ].


The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation.<ref>{{cite book |author=P. Darche |url=https://books.google.com/books?id=rLC9zQEACAAJ |title=Microprocessor: Prolegomenes - Calculation and Storage Functions - Calculation Models and Computer |year=2020 |isbn=9781786305633 |page=59| publisher=John Wiley & Sons }}</ref><ref>{{cite book |author1=B. Jacob |url=https://books.google.com/books?id=SrP3aWed-esC |title=Memory Systems: Cache, DRAM, Disk |author2=S. W. Ng |author3=D. T. Wang |publisher=Morgan Kaufmann |year=2008 |isbn=9780080553849 |page=324}}</ref> In 1992 Samsung released KM48SL2000, which had a capacity of 16{{nbsp}}].<ref name="electronic-design">{{cite journal |title=Electronic Design |journal=] |date=1993 |volume=41 |issue=15–21 |url=https://books.google.com/books?id=QmpJAQAAIAAJ |publisher=Hayden Publishing Company |quote=The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.}}</ref><ref>{{cite web |title=KM48SL2000-7 Datasheet |url=https://www.datasheetarchive.com/KM48SL2000-7-datasheet.html |publisher=] |access-date=19 June 2019 |date=August 1992}}</ref> and mass-produced in 1993.<ref name="electronic-design"/> The first commercial ] (] SDRAM) memory chip was Samsung's 64{{nbsp}}Mbit DDR SDRAM chip, released in June 1998.<ref>{{cite news |title=Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-develops-first-128mb-sdram-with-ddr-sdr-manufacturing-option/ |access-date=23 June 2019 |work=] |publisher=] |date=10 February 1999}}</ref> ] (graphics DDR) is a form of DDR ] (synchronous graphics RAM), which was first released by Samsung as a 16{{nbsp}}Mbit memory chip in 1998.<ref>{{cite news |title=Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs |url=https://www.samsung.com/semiconductor/insights/news-events/samsung-electronics-comes-out-with-super-fast-16m-ddr-sgrams/ |access-date=23 June 2019 |work=] |publisher=] |date=17 September 1998}}</ref>
==== Shadow RAM ====
Sometimes, the contents of a ROM chip are copied to SRAM or DRAM to allow for shorter access times (as ROM may be slower). The ROM chip is then disabled while the initialized memory locations are switched in on the same block of addresses (often write-protected). This process, sometimes called ''shadowing'', is fairly common in both computers and ].


==Types==
As a common example, the ] in typical personal computers often has an option called “use shadow BIOS” or similar. When enabled, functions relying on data from the BIOS’s ROM will instead use DRAM locations (most can also toggle shadowing of video card ROM or other ROM sections). Depending on the system, this may or may not result in increased performance. On some systems the benefit may be hypothetical because the BIOS is not used after booting in favor of direct hardware access. Of course, somewhat less free memory is available when shadowing is enabled.<ref> {{cite web |url=http://hardwarehell.com/articles/shadowram.htm|title=Shadow Ram|accessdate=2007-07-24 }}</ref>
The two widely used forms of modern RAM are ] (SRAM) and ] (DRAM). In SRAM, a ] is stored using the state of a six-] ], typically using six MOSFETs. This form of RAM is more expensive to produce, but is generally faster and requires less dynamic power than DRAM. In modern computers, SRAM is often used as ]. DRAM stores a bit of data using a transistor and ] pair (typically a MOSFET and ], respectively),<ref>{{cite book |last1=Sze |first1=Simon M. |author1-link=Simon Sze |title=Semiconductor Devices: Physics and Technology |date=2002 |publisher=] |isbn=0-471-33372-7 |page=214 |edition=2nd |url=http://www.fulviofrisone.com/attachments/article/453/Semiconductor.Devices_Physics.Technology_Sze.2ndEd_Wiley_2002.pdf}}</ref> which together comprise a DRAM cell. The capacitor holds a high or low charge (1 or 0, respectively), and the transistor acts as a switch that lets the control circuitry on the chip read the capacitor's state of charge or change it. As this form of memory is less expensive to produce than static RAM, it is the predominant form of computer memory used in modern computers.


Both static and dynamic RAM are considered ''volatile'', as their state is lost or reset when power is removed from the system. By contrast, ] (ROM) stores data by permanently enabling or disabling selected transistors, such that the memory cannot be altered. Writable variants of ROM (such as ] and ]) share properties of both ROM and RAM, enabling data to ] without power and to be updated without requiring special equipment. ] (which can be either SRAM or DRAM) includes special circuitry to detect and/or correct random faults (memory errors) in the stored data, using ]s or ].
==Recent developments==
Several new types of ], which will preserve data while powered down, are under development. The technologies used include ryan ]s and approaches utilizing the ]. Amongst the 1st generation MRAM, a 128 ] (128&nbsp;×&nbsp;2<sup>10</sup> bytes) ] (MRAM) chip was manufactured with 0.18&nbsp;µm technology in the summer of 2003. In June 2004, ] unveiled a 16&nbsp;] (16&nbsp;×&nbsp;2<sup>20</sup> bytes) prototype again based on 0.18&nbsp;µm technology. There are two 2nd generation techniques currently in development: ] (TAS)<ref>The Emergence of Practical MRAM http://www.crocus-technology.com/pdf/BH%20GSA%20Article.pdf</ref> which is being developed by ], and ] (STT) on which ], ], ], and several other companies are working<ref>http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=218000269</ref>. ] built a functioning carbon nanotube memory prototype 10&nbsp;] (10&nbsp;×&nbsp;2<sup>30</sup> bytes) array in 2004. Whether some of these technologies will be able to eventually take a significant market share from either DRAM, SRAM, or flash-memory technology, however, remains to be seen.


In general, the term ''RAM'' refers solely to solid-state memory devices (either DRAM or SRAM), and more specifically the main memory in most computers. In optical storage, the term ] is somewhat of a misnomer since, it is not random access; it behaves much like a hard disc drive if somewhat slower. Aside, unlike ] or ], DVD-RAM does not need to be erased before reuse.
Since 2006, "]s" (based on flash memory) with capacities exceeding 64 gigabytes and performance far exceeding traditional disks have become available. This development has started to blur the definition between traditional random access memory and "disks", dramatically reducing the difference in performance.
Also in development is research being done in the field of plastic magnets, which switch magnetic polarities based on ].
{{Citation needed|date=May 2009}}


==Memory cell==
Some kinds of random-access memory, such as "EcoRAM", are specifically designed for ]s, where ] is more important than speed.
{{main|Memory cell (computing)}}
<ref>
The memory cell is the fundamental building block of ]. The memory cell is an ] that stores one ] of binary information and it must be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

by Heather Clancy 2008
In SRAM, the memory cell is a type of ] circuit, usually implemented using ]s. This means that SRAM requires very low power when not being accessed, but it is expensive and has low storage density.
</ref>

A second type, DRAM, is based around a capacitor. Charging and discharging this capacitor can store a "1" or a "0" in the cell. However, the charge in this capacitor slowly leaks away, and must be refreshed periodically. Because of this refresh process, DRAM uses more power, but it can achieve greater storage densities and lower unit costs compared to SRAM.
{| style="text-align:center; margin: 1em auto 1em auto"
|]||]
|}

==Addressing==
To be useful, memory cells must be readable and writable. Within the RAM device, multiplexing and demultiplexing circuitry is used to select memory cells. Typically, a RAM device has a set of address lines <math>A_0, A_1,...A_n</math>, and for each combination of bits that may be applied to these lines, a set of memory cells are activated. Due to this addressing, RAM devices virtually always have a memory capacity that is a power of two.

Usually several memory cells share the same address. For example, a 4 bit "wide" RAM chip has four memory cells for each address. Often the width of the memory and that of the microprocessor are different, for a 32 bit microprocessor, eight 4 bit RAM chips would be needed.

Often more addresses are needed than can be provided by a device. In that case, external multiplexors to the device are used to activate the correct device that is being accessed. RAM is often byte addressable, although it is also possible to make RAM that is word-addressable.<ref>{{cite book | url=https://books.google.com/books?id=QGPHAl9GE-IC&dq=size+of+a+memory+address&pg=PA321 | isbn=978-0-7637-3769-6 | title=The Essentials of Computer Organization and Architecture | date=2006 | publisher=Jones & Bartlett Learning }}</ref><ref>{{cite book | url=https://books.google.com/books?id=-vQCEAAAQBAJ | title=Foundations of Computer Technology | isbn=978-1-000-15371-2 | last1=Anderson | first1=Alexander John | date=25 October 2020 | publisher=CRC Press }}</ref>

==Memory hierarchy==
{{main|Memory hierarchy}}
One can read and over-write data in RAM. Many computer systems have a memory hierarchy consisting of ]s, on-] ] caches, external ], ], ] systems and ] or ] on a hard drive. This entire pool of memory may be referred to as "RAM" by many developers, even though the various subsystems can have very different ]s, violating the original concept behind the ''random access'' term in RAM. Even within a hierarchy level such as DRAM, the specific row, column, bank, ], channel, or ] organization of the components make the access time variable, although not to the extent that access time to rotating ] or a tape is variable. The overall goal of using a memory hierarchy is to obtain the fastest possible average access time while minimizing the total cost of the entire memory system (generally, the memory hierarchy follows the access time with the fast CPU registers at the top and the slow hard drive at the bottom).

In many modern personal computers, the RAM comes in an easily upgraded form of modules called ]s or DRAM modules about the size of a few sticks of chewing gum. These can be quickly replaced should they become damaged or when changing needs demand more storage capacity. As suggested above, smaller amounts of RAM (mostly SRAM) are also integrated in the ] and other ] on the ], as well as in hard-drives, ]s, and several other parts of the computer system.

==Other uses of RAM==
] stick of laptop RAM, roughly half the size of ]]]
In addition to serving as temporary storage and working space for the operating system and applications, RAM is used in numerous other ways.

===Virtual memory===
{{main|Virtual memory}}
Most modern operating systems employ a method of extending RAM capacity, known as "virtual memory". A portion of the computer's ] is set aside for a ''paging file'' or a ''scratch partition'', and the combination of physical RAM and the paging file form the system's total memory. (For example, if a computer has 2&nbsp;GB (1024<sup>3</sup> B) of RAM and a 1&nbsp;GB page file, the operating system has 3&nbsp;GB total memory available to it.) When the system runs low on physical memory, it can "]" portions of RAM to the paging file to make room for new data, as well as to read previously swapped information back into RAM. Excessive use of this mechanism results in ] and generally hampers overall system performance, mainly because hard drives are far slower than RAM.

===RAM disk===
{{main|RAM drive}}
Software can "partition" a portion of a computer's RAM, allowing it to act as a much faster hard drive that is called a ]. A RAM disk loses the stored data when the computer is shut down, unless memory is arranged to have a standby battery source, or changes to the RAM disk are written out to a nonvolatile disk. The RAM disk is reloaded from the physical disk upon RAM disk initialization.

===Shadow RAM===
Sometimes, the contents of a relatively slow ROM chip are copied to read/write memory to allow for shorter access times. The ROM chip is then disabled while the initialized memory locations are switched in on the same block of addresses (often write-protected). This process, sometimes called ''shadowing'', is fairly common in both computers and ].

As a common example, the ] in typical personal computers often has an option called "use shadow BIOS" or similar. When enabled, functions that rely on data from the BIOS's ROM instead use DRAM locations (most can also toggle shadowing of video card ROM or other ROM sections). Depending on the system, this may not result in increased performance, and may cause incompatibilities. For example, some hardware may be inaccessible to the ] if shadow RAM is used. On some systems the benefit may be hypothetical because the BIOS is not used after booting in favor of direct hardware access. Free memory is reduced by the size of the shadowed ROMs.<ref>{{cite web|url=http://hardwarehell.com/articles/shadowram.htm|title=Shadow Ram|access-date=2007-07-24|url-status=live|archive-url=https://web.archive.org/web/20061029162135/http://hardwarehell.com/articles/shadowram.htm|archive-date=2006-10-29}}</ref>


==Memory wall== ==Memory wall==
The "memory wall" is the growing disparity of speed between CPU and memory outside the CPU chip. An important reason for this disparity is the limited communication bandwidth beyond chip boundaries. From 1986 to 2000, ] speed improved at an annual rate of 55% while memory speed only improved at 10%. Given these trends, it was expected that memory latency would become an overwhelming ] in computer performance. <ref>The term was coined in .</ref> The ''''memory wall''' is the growing disparity of speed between CPU and the response time of memory (known as ]) outside the CPU chip. An important reason for this disparity is the limited communication bandwidth beyond chip boundaries, which is also referred to as ''bandwidth wall''. From 1986 to 2000, ] speed improved at an annual rate of 55% while off-chip memory response time only improved at 10%. Given these trends, it was expected that memory latency would become an overwhelming ] in computer performance.<ref>The term was coined in {{cite web |url=http://www.eecs.ucf.edu/~lboloni/Teaching/EEL5708_2006/slides/wulf94.pdf |title=Archived copy |access-date=2011-12-14 |url-status=live |archive-url=https://web.archive.org/web/20120406111104/http://www.eecs.ucf.edu/~lboloni/Teaching/EEL5708_2006/slides/wulf94.pdf |archive-date=2012-04-06 }}.</ref>


Another reason for the disparity is the enormous increase in the size of memory since the start of the PC revolution in the 1980s. Originally, PCs contained less than 1 mebibyte of RAM, which often had a response time of 1 CPU clock cycle, meaning that it required 0 wait states. Larger memory units are inherently slower than smaller ones of the same type, simply because it takes longer for signals to traverse a larger circuit. Constructing a memory unit of many gibibytes with a response time of one clock cycle is difficult or impossible. Today's CPUs often still have a mebibyte of 0 wait state cache memory, but it resides on the same chip as the CPU cores due to the bandwidth limitations of chip-to-chip communication. It must also be constructed from static RAM, which is far more expensive than the dynamic RAM used for larger memories. Static RAM also consumes far more power.
Currently, CPU speed improvements have slowed significantly partly due to major physical barriers and partly because current CPU designs have already hit the memory wall in some sense. Intel summarized these causes in their
<blockquote>
“First of all, as chip geometries shrink and clock frequencies rise, the transistor leakage current increases, leading to excess power consumption and heat (more on power consumption below). Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called ]), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, ] (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.”
</blockquote>


CPU speed improvements slowed significantly partly due to major physical barriers and partly because current CPU designs have already hit the memory wall in some sense. ] summarized these causes in a 2005 document.<ref>{{Cite web |title= Platform 2015: Intel Processor and Platform Evolution for the Next Decade |date= March 2, 2005 |url= http://epic.hpi.uni-potsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdf |url-status= live |archive-url= https://web.archive.org/web/20110427072037/http://epic.hpi.uni-potsdam.de/pub/Home/TrendsAndConceptsII2010/HW_Trends_borkar_2015.pdf |archive-date= April 27, 2011 }}</ref>
The RC delays in signal transmission were also noted in which projects a maximum of 12.5% average annual CPU performance improvement between 2000 and 2014. The data on clearly shows a slowdown in performance improvements in recent processors. However, Intel's new processors, ] (codenamed Conroe) show a significant improvement over previous ] processors; due to a more efficient architecture, performance increased while clock rate actually decreased.


<blockquote>First of all, as chip geometries shrink and clock frequencies rise, the transistor ] increases, leading to excess power consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called ]), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, ] (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.</blockquote>
==Security concerns==
Contrary to simple models (and perhaps common belief), the contents of modern SDRAM modules are not lost immediately when the computer is shut down; instead, the contents fade away, a process that takes only seconds at room temperatures, but which can be extended to minutes at low temperatures. It is therefore possible to recover an encryption key stored in ordinary working memory (i.e. the SDRAM modules).<ref></ref> This is sometimes referred to as a ], aka ice-man attack.


The RC delays in signal transmission were also noted in "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures"<ref>{{Cite conference |first1=Vikas |last1=Agarwal |first2=M. S. |last2=Hrishikesh |first3=Stephen W. |last3=Keckler |first4=Doug |last4=Burger |title=Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures |url=http://www.cs.utexas.edu/users/cart/trips/publications/isca00.pdf |conference=27th Annual International Symposium on Computer Architecture |conference-url=https://dl.acm.org/citation.cfm?id=339647 |book-title=Proceedings of the 27th Annual International Symposium on Computer Architecture |location=Vancouver, BC |date=June 10–14, 2000 |access-date=14 July 2018}}</ref> which projected a maximum of 12.5% average annual CPU performance improvement between 2000 and 2014.
== See also ==

{{commons|RAM}}
A different concept is the processor-memory performance gap, which can be addressed by ] that reduce the distance between the logic and memory aspects that are further apart in a 2D chip.<ref>{{cite book |page=790 |url=https://books.google.com/books?id=1PgYS7zDCM8C&q=processor-memory+performance+gap&pg=PA790 |access-date=March 31, 2014 |title=Nanoelectronics and Information Technology |author=Rainer Waser |publisher=John Wiley & Sons |year=2012 |url-status=live |archive-url=https://web.archive.org/web/20160801114150/https://books.google.com/books?id=1PgYS7zDCM8C&pg=PA790&dq=processor-memory+performance+gap&hl=en&sa=X&ei=jeM5U93YAqTr2QWc74A4&ved=0CDYQ6AEwAg#v=onepage&q=processor-memory%20performance%20gap&f=false |archive-date=August 1, 2016 |isbn = 9783527409273|author-link = Rainer Waser}}</ref> Memory subsystem design requires a focus on the gap, which is widening over time.<ref>{{cite book |url=https://books.google.com/books?id=0IY7LW5J4JgC&q=processor-memory+performance+gap&pg=PA109 |page=109 |access-date=March 31, 2014 |title=Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings |author=Chris Jesshope and Colin Egan |publisher=Springer |date=2006 |url-status=live |archive-url=https://web.archive.org/web/20160801135254/https://books.google.com/books?id=0IY7LW5J4JgC&pg=PA109&dq=processor-memory+performance+gap&hl=en&sa=X&ei=jeM5U93YAqTr2QWc74A4&ved=0CEkQ6AEwBg#v=onepage&q=processor-memory%20performance%20gap&f=false |archive-date=August 1, 2016 |isbn=9783540400561 }}</ref> The main method of bridging the gap is the use of ]; small amounts of high-speed memory that houses recent operations and instructions nearby the processor, speeding up the execution of those operations or instructions in cases where they are called upon frequently. Multiple levels of caching have been developed to deal with the widening gap, and the performance of high-speed modern computers relies on evolving caching techniques.<ref>{{cite book |url=https://books.google.com/books?id=7i9Z69lrYBoC&q=processor-memory+performance+gap&pg=PA90 |pages=90–91 |access-date=March 31, 2014 |title=Multiprocessor Systems-on-chips |author=Ahmed Amine Jerraya and Wayne Wolf |publisher=Morgan Kaufmann |year=2005 |url-status=live |archive-url=https://web.archive.org/web/20160801105357/https://books.google.com/books?id=7i9Z69lrYBoC&pg=PA90&dq=processor-memory+performance+gap&hl=en&sa=X&ei=jeM5U93YAqTr2QWc74A4&ved=0CFMQ6AEwCA#v=onepage&q=processor-memory%20performance%20gap&f=false |archive-date=August 1, 2016 |isbn=9780123852519 }}</ref> There can be up to a 53% difference between the growth in speed of processor and the lagging speed of main memory access.<ref>{{cite book |url=https://books.google.com/books?id=f0pJYJQMlmoC&q=processor-memory+performance+gap&pg=PA529 |page=529 |access-date=March 31, 2014 |title=Experimental and Efficient Algorithms: Third International Workshop, WEA 2004, Angra Dos Reis, Brazil, May 25-28, 2004, Proceedings, Volume 3 |author=Celso C. Ribeiro and Simone L. Martins |publisher=Springer |year=2004 |url-status=live |archive-url=https://web.archive.org/web/20160801092734/https://books.google.com/books?id=f0pJYJQMlmoC&pg=PA529&dq=processor-memory+performance+gap&hl=en&sa=X&ei=1eM5U7veEaTx2QXM2oDYCw&ved=0CCwQ6AEwADgU#v=onepage&q=processor-memory%20performance%20gap&f=false |archive-date=August 1, 2016 |isbn=9783540220671 }}</ref>

] have continued to increase in speed, from ~400&nbsp;Mbit/s via ] in 2012 up to ~7&nbsp;GB/s via ]/] in 2024, closing the gap between RAM and hard disk speeds, although RAM continues to be an order of magnitude faster, with single-lane ] 8000MHz capable of 128&nbsp;GB/s, and modern ] even faster. Fast, cheap, ] solid state drives have replaced some functions formerly performed by RAM, such as holding certain data for immediate availability in ]s - 1 ] of SSD storage can be had for $200, while 1&nbsp;TB of RAM would cost thousands of dollars.<ref>{{Cite web|url=https://www.minitool.com/news/ssd-prices-fall.html|title=SSD Prices Continue to Fall, Now Upgrade Your Hard Drive!|date=2018-09-03|website=MiniTool|language=en-us|access-date=2019-03-28}}</ref><ref>{{Cite web|url=https://www.digitaltrends.com/computing/ram-prices-are-increasing-until-third-quarter-2017/|title=If you're buying or upgrading your PC, expect to pay more for RAM|last=Coppock|first=Mark|date=31 January 2017|website=www.digitaltrends.com|access-date=2019-03-28}}</ref>

==Timeline==
{{See also|Flash memory#Timeline|Read-only memory#Timeline|Transistor count#Memory}}

===SRAM===
{| class="wikitable sortable" style="text-align:center"
|+ ] (SRAM)
|-
! Date of introduction
! Chip name
! Capacity (]s)
! ]
! SRAM type
! Manufacturer(s)
! data-sort-type="number" |]
! ]
! {{Abbr|Ref|Reference(s)}}
|-
|{{dts|1963|3}}
|{{n/a}}
|]
|{{?}}
|] (])
|]
|{{n/a}}
|{{n/a}}
| rowspan="2" |<ref name="computerhistory1966">{{cite web |title=1966: Semiconductor RAMs Serve High-speed Storage Needs |url=https://www.computerhistory.org/siliconengine/semiconductor-rams-serve-high-speed-storage-needs/ |website=] |access-date=19 June 2019}}</ref>
|-
| rowspan="3" |1965
|{{?}}
|]
|{{?}}
|]
|]
|{{?}}
|{{n/a}}
|-
|SP95
|]
|{{?}}
|Bipolar
|IBM
|{{?}}
|{{n/a}}
|<ref>{{cite book |title=IBM first in IC memory |url=https://www.computerhistory.org/collections/catalog/102770626 |website=] |year=1965 |publisher=IBM Corporation |access-date=19 June 2019}}</ref>
|-
|{{?}}
|]
|{{?}}
|]
|Fairchild
|{{?}}
|]
|<ref name="Sah1303">{{cite journal |last=Sah |first=Chih-Tang |author-link=Chih-Tang Sah |title=Evolution of the MOS transistor-from conception to VLSI |journal=] |date=October 1988 |volume=76 |issue=10 |pages=1280–1326 (1303) |doi=10.1109/5.16328 |url=http://www.dejazzer.com/ece723/resources/Evolution_of_the_MOS_transistor.pdf |issn=0018-9219|bibcode=1988IEEEP..76.1280S }}</ref>
|-
| rowspan="2" |1966
|TMC3162
|16
|{{?}}
|Bipolar (])
|]
|{{?}}
|{{n/a}}
|<ref name="computerhistory1970"/>
|-
|{{?}}
|{{?}}
|{{?}}
|MOSFET
|]
|{{?}}
|{{?}}
|<ref name="shmj-mos"/>
|-
|rowspan="3" | 1968
|rowspan="3" | {{?}}
|64
|{{?}}
|MOSFET
|Fairchild
|{{?}}
|PMOS
|rowspan="2" | <ref name="shmj-mos"/>
|-
|144
|{{?}}
|MOSFET
|NEC
|{{?}}
|]
|-
|]
|{{?}}
|MOSFET
|IBM
|{{?}}
|NMOS
|<ref name="Sah1303"/>
|-
| rowspan="2" |1969
|{{?}}
|]
|{{?}}
|Bipolar
|IBM
|{{?}}
|{{n/a}}
|<ref name="computerhistory1966"/>
|-
|1101
|]
|850 ]
|MOSFET
|]
|12,000 ]
|PMOS
|<ref name="Intel-Product-Timeline"/><ref name="shmj-1970s-sram">{{cite web |title=1970s: SRAM evolution |url=http://www.shmj.or.jp/english/pdf/ic/exhibi724E.pdf |website=Semiconductor History Museum of Japan |access-date=27 June 2019}}</ref><ref name="Pimbley">{{cite book |last1=Pimbley |first1=J. |title=Advanced CMOS Process Technology |date=2012 |publisher=] |isbn=9780323156806 |page=7 |url=https://books.google.com/books?id=8EUWHSqevQoC&pg=PA7}}</ref><ref>{{Cite web|url=https://www.intel-vintage.info/intelmemory.htm|title=Intel Memory|website=Intel Vintage|access-date=2019-07-06|ref=intel-memory|archive-date=2022-03-19|archive-url=https://web.archive.org/web/20220319073833/https://www.intel-vintage.info/intelmemory.htm|url-status=dead}}</ref>
|-
|1972
|2102
|1 ]
|{{?}}
|MOSFET
|Intel
|{{?}}
|NMOS
|<ref name="Intel-Product-Timeline"/>
|-
| rowspan="2" |1974
|5101
|1 kbit
|800 ns
|MOSFET
|Intel
|{{?}}
|]
|<ref name="Intel-Product-Timeline"/><ref name="Intel-1978-3">{{cite book |title=Component Data Catalog |date=1978 |publisher=] |page=3 |url=http://bitsavers.trailing-edge.com/components/intel/_dataBooks/1978_Intel_Component_Data_Catalog.pdf |access-date=27 June 2019}}</ref>
|-
|2102A
|1 kbit
|350 ns
|MOSFET
|Intel
|{{?}}
|NMOS (])
|<ref name="Intel-Product-Timeline"/><ref>{{cite web |title=Silicon Gate MOS 2102A |url=https://drive.google.com/file/d/0B9rh9tVI0J5mMmZlYWRlMDQtNDYzYS00OWJkLTg4YzYtZDYzMzc5Y2ZlYmVk/view |publisher=] |access-date=27 June 2019}}</ref>
|-
|1975
|2114
|4 kbit
|450 ns
|MOSFET
|Intel
|{{?}}
|NMOS
|<ref name="Intel-Product-Timeline"/><ref name="Intel-1978-3"/>
|-
| rowspan="2" |1976
|2115
|1 kbit
|70 ns
|MOSFET
|Intel
|{{?}}
|NMOS (])
|<ref name="Intel-Product-Timeline"/><ref name="shmj-1970s-sram"/>
|-
|2147
|4 kbit
|55 ns
|MOSFET
|Intel
|{{?}}
|NMOS (HMOS)
|<ref name="Intel-Product-Timeline"/><ref name="hitachi-cmos">{{cite web |title=1978: Double-well fast CMOS SRAM (Hitachi) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf |website=Semiconductor History Museum of Japan |access-date=5 July 2019}}</ref>
|-
|1977
|{{?}}
|4 kbit
|{{?}}
|MOSFET
|]
|{{?}}
|CMOS
|<ref name="shmj-1970s-sram"/>
|-
| rowspan="2" |1978
|HM6147
|4 kbit
|55 ns
|MOSFET
|]
|]
|CMOS (])
|<ref name="hitachi-cmos"/>
|-
|TMS4016
|16 kbit
|{{?}}
|MOSFET
|]
|{{?}}
|NMOS
|<ref name="shmj-1970s-sram"/>
|-
|rowspan="2" | 1980
|rowspan="2" | {{?}}
|16 kbit
|{{?}}
|MOSFET
|Hitachi, Toshiba
|rowspan="2" | {{?}}
|rowspan="2" | CMOS
|rowspan="2" | <ref name="stol"/>
|-
|64 kbit
|{{?}}
|MOSFET
|]
|-
|1981
|{{?}}
|16 kbit
|{{?}}
|MOSFET
|Texas Instruments
|2,500&nbsp;nm
|NMOS
|<ref name="stol"/>
|-
|{{dts|1981|10}}
|{{?}}
|4 kbit
|18 ns
|MOSFET
|Matsushita, Toshiba
|2,000&nbsp;nm
|CMOS
|<ref>{{cite journal |last1=Isobe |first1=Mitsuo |last2=Uchida |first2=Yukimasa |last3=Maeguchi |first3=Kenji |last4=Mochizuki |first4=T. |last5=Kimura |first5=M. |last6=Hatano |first6=H. |last7=Mizutani |first7=Y. |last8=Tango |first8=H. |title=An 18 ns CMOS/SOS 4K static RAM |journal=] |date=October 1981 |volume=16 |issue=5 |pages=460–465 |doi=10.1109/JSSC.1981.1051623|bibcode=1981IJSSC..16..460I |s2cid=12992820 }}</ref>
|-
|1982
|{{?}}
|64 kbit
|{{?}}
|MOSFET
|Intel
|]
|NMOS (HMOS)
|<ref name="stol"/>
|-
|{{dts|1983|2}}
|{{?}}
|64 kbit
|50 ns
|MOSFET
|]
|{{?}}
|CMOS
|<ref>{{cite book |last1=Yoshimoto |first1=M. |last2=Anami |first2=K. |last3=Shinohara |first3=H. |last4=Yoshihara |first4=T. |last5=Takagi |first5=H. |last6=Nagao |first6=S. |last7=Kayano |first7=S. |last8=Nakano |first8=T. |title=1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |chapter=A 64Kb full CMOS RAM with divided word line structure |date=1983 |volume=XXVI |pages=58–59 |doi=10.1109/ISSCC.1983.1156503|s2cid=34837669 }}</ref>
|-
|1984
|{{?}}
|256 kbit
|{{?}}
|MOSFET
|Toshiba
|1,200&nbsp;nm
|CMOS
|<ref name="stol"/><ref name="Pimbley"/>
|-
|1987
|{{?}}
|1 ]
|{{?}}
|MOSFET
|], Hitachi, ], Toshiba
|{{?}}
|CMOS
|<ref name="stol"/>
|-
|{{dts|1987|12}}
|{{?}}
|256 kbit
|10 ns
|]
|Texas Instruments
|800&nbsp;nm
|]
|<ref>{{cite book |last1=Havemann |first1=Robert H. |last2=Eklund |first2=R. E. |last3=Tran |first3=Hiep V. |last4=Haken |first4=R. A. |last5=Scott |first5=D. B. |last6=Fung |first6=P. K. |last7=Ham |first7=T. E. |last8=Favreau |first8=D. P. |last9=Virkus |first9=R. L. |title=1987 International Electron Devices Meeting |chapter=An 0.8 μm 256K BiCMOS SRAM technology |date=December 1987 |pages=841–843 |doi=10.1109/IEDM.1987.191564|s2cid=40375699 }}</ref>
|-
|1990
|{{?}}
|4 Mbit
|15{{ndash}}23 ns
|MOSFET
|NEC, Toshiba, Hitachi, Mitsubishi
|{{?}}
|rowspan="2" | CMOS
|rowspan="2" | <ref name="stol"/>
|-
|1992
|{{?}}
|16 Mbit
|12{{ndash}}15 ns
|MOSFET
|], NEC
|400&nbsp;nm
|-
|{{dts|1994|12}}
|{{?}}
|512 kbit
|2.5 ns
|MOSFET
|IBM
|{{?}}
|CMOS (])
|<ref>{{cite journal |last1=Shahidi |first1=Ghavam G. |author1-link=Ghavam Shahidi |last2=Davari |first2=Bijan |author2-link=Bijan Davari |last3=Dennard |first3=Robert H. |author3-link=Robert H. Dennard |last4=Anderson |first4=C. A. |last5=Chappell |first5=B. A. |last6=Chappell |first6=T. I. |last7=Comfort |first7=J. H. |last8=Franch |first8=R. L. |last9=McFarland |first9=P. A. |last10=Neely |first10=J. S. |last11=Ning |first11=T. H. |last12=Polcari |first12=M. R. |last13=Warnock |first13=J. D. |display-authors=5 |title=A room temperature 0.1 μm CMOS on SOI |journal=] |date=December 1994 |volume=41 |issue=12 |pages=2405–2412 |doi=10.1109/16.337456|bibcode=1994ITED...41.2405S |s2cid=108832941 }}</ref>
|-
| rowspan="2" |1995
| rowspan="2" |{{?}}
|4 Mbit
|6 ns
|] (])
|Hitachi
|100&nbsp;nm
|CMOS
|<ref name="smithsonian-japan"/>
|-
|256 Mbit
|{{?}}
|MOSFET
|]
|{{?}}
|CMOS
|<ref name="hynix90s-skhynix.com">{{cite web |title=History: 1990s |url=https://www.skhynix.com/eng/about/history1990.jsp |website=] |access-date=6 July 2019 |archive-date=5 February 2021 |archive-url=https://web.archive.org/web/20210205032928/https://www.skhynix.com/eng/about/history1990.jsp |url-status=dead }}</ref>
|}

===DRAM===
{| class="wikitable sortable" style="text-align:center"
|+ ] (DRAM)
|-
! Date of introduction
! Chip name
! Capacity (]s)
! DRAM type
! Manufacturer(s)
! data-sort-type="number" |]
!]
! data-sort-type="number" | Area
! {{Abbr|Ref|Reference(s)}}
|-
|1965
|{{n/a}}
|]
|DRAM (])
|]
|{{n/a}}
|{{n/a}}
|{{n/a}}
|<ref name="bc-spec">{{cite web|url=http://www.oldcalculatormuseum.com/s-toshbc1411.html|title=Spec Sheet for Toshiba "TOSCAL" BC-1411|website=Old Calculator Web Museum|access-date=8 May 2018|url-status=live|archive-url=https://web.archive.org/web/20170703071307/http://www.oldcalculatormuseum.com/s-toshbc1411.html|archive-date=3 July 2017}}</ref><ref name="bc"> {{webarchive|url=https://web.archive.org/web/20070520202433/http://www.oldcalculatormuseum.com/toshbc1411.html |date=2007-05-20 }}</ref>
|-
|1967
|{{n/a}}
|1 bit
|DRAM (cell)
|]
|{{n/a}}
|]
|{{n/a}}
|<ref name="Robert Dennard">{{cite web |title=Robert Dennard |url=https://www.britannica.com/biography/Robert-Dennard |website=] |access-date=8 July 2019}}</ref><ref name="shmj-mos">{{cite web |title=Late 1960s: Beginnings of MOS memory |url=http://www.shmj.or.jp/english/pdf/ic/exhibi718E.pdf |website=Semiconductor History Museum of Japan |date=2019-01-23 |access-date=27 June 2019}}</ref>
|-
|1968
|{{?}}
|]
|DRAM (])
|]
|{{?}}
|]
|{{?}}
|<ref name="computerhistory1970">{{cite web |title=1970: Semiconductors compete with magnetic cores |url=https://www.computerhistory.org/storageengine/semiconductors-compete-with-magnetic-cores/ |website=] |access-date=19 June 2019}}</ref>
|-
|1969
|{{n/a}}
|1 bit
|DRAM (cell)
|]
|{{n/a}}
|PMOS
|{{n/a}}
|<ref name="shmj-mos"/>
|-
| rowspan="2" |1970
|]
|1 ]
|DRAM (IC)
|Intel, ]
|{{?}}
|PMOS
|{{?}}
|<ref name="shmj-mos"/>
|-
|]
|1 kbit
|DRAM
|Intel
|8,000 ]
|PMOS
|10&nbsp;mm<sup>2</sup>
|<ref name="Intel2003">{{cite web |title=Intel: 35 Years of Innovation (1968–2003) |url=https://www.intel.com/Assets/PDF/General/35yrs.pdf |publisher=Intel |year=2003 |access-date=26 June 2019}}</ref><ref name="HC"> history-computer.com</ref><ref name="Lojek-1103">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=] |isbn=9783540342588 |pages=362–363 |url=https://books.google.com/books?id=2cu1Oh_COv8C&pg=PA362 |quote=The i1103 was manufactured on a 6-mask silicon-gate P-MOS process with 8 μm minimum features. The resulting product had a 2,400 μm<sup>2</sup> memory cell size, a die size just under 10 mm<sup>2</sup>, and sold for around $21.}}</ref>
|-
| rowspan="2" |1971
|μPD403
|1 kbit
|DRAM
|]
|{{?}}
|]
|{{?}}
|<ref>{{cite web |title=Manufacturers in Japan enter the DRAM market and integration densities are improved |url=http://www.shmj.or.jp/english/pdf/ic/exhibi745E.pdf |website=Semiconductor History Museum of Japan |access-date=27 June 2019}}</ref>
|-
|{{?}}
|2 kbit
|DRAM
|]
|{{?}}
|PMOS
|13&nbsp;mm<sup>2</sup>
|<ref name="Gealow">{{cite web |last1=Gealow |first1=Jeffrey Carl |title=Impact of Processing Technology on DRAM Sense Amplifier Design |url=https://core.ac.uk/download/pdf/4426308.pdf |publisher=] |via=] |date=10 August 1990 |pages=149–166 |access-date=25 June 2019}}</ref>
|-
|1972
|2107
|4 kbit
|DRAM
|Intel
|{{?}}
|NMOS
|{{?}}
|<ref name="Intel-Product-Timeline">{{cite web|url=http://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf|title=A chronological list of Intel products. The products are sorted by date.|date=July 2005|work=Intel museum|publisher=Intel Corporation|archive-url=https://web.archive.org/web/20070809053720/http://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf|archive-date=August 9, 2007|access-date=July 31, 2007}}</ref><ref>{{cite web |title=Silicon Gate MOS 2107A |url=https://drive.google.com/file/d/0B9rh9tVI0J5mMDJjOGZkNzUtNzMxMS00ZWM5LWIzNjEtZTg1MDZiNjM3ZDBm/view |publisher=] |access-date=27 June 2019}}</ref>
|-
|1973
|{{?}}
|8 kbit
|DRAM
|IBM
|{{?}}
|PMOS
|19&nbsp;mm<sup>2</sup>
|<ref name="Gealow"/>
|-
|1975
|2116
|16 kbit
|DRAM
|Intel
|{{?}}
|NMOS
|{{?}}
|<ref>{{cite web |title=One of the Most Successful 16K Dynamic RAMs: The 4116 |url=http://smithsonianchips.si.edu/augarten/p50.htm |url-status=dead |website=] |publisher=] |access-date=20 June 2019 |archive-url=https://web.archive.org/web/20230531180053/https://smithsonianchips.si.edu/augarten/p50.htm |archive-date=2023-05-31}}</ref><ref name="computerhistory1970"/>
|-
|1977
|{{?}}
|64 kbit
|DRAM
|]
|{{?}}
|NMOS
|35&nbsp;mm<sup>2</sup>
|<ref name="Gealow"/>
|-
| rowspan="2" |1979
|MK4816
|16 kbit
|]
|]
|{{?}}
|NMOS
|{{?}}
|<ref>{{cite book |title=Memory Data Book And Designers Guide |date=March 1979 |publisher=] |pages=9 & 183 |url=http://www.bitsavers.org/components/mostek/_dataBooks/1979_Mostek_Memory_Data_Book_and_Designers_Guide_Mar79.pdf}}</ref>
|-
|{{?}}
|64 kbit
|DRAM
|]
|{{?}}
|]
|25&nbsp;mm<sup>2</sup>
|<ref name="Gealow"/>
|-
|1980
|{{?}}
|256 kbit
|DRAM
|NEC, NTT
|1,000{{ndash}}]
|NMOS
|34{{ndash}}42&nbsp;mm<sup>2</sup>
|<ref name="Gealow"/>
|-
|1981
|{{?}}
|288 kbit
|DRAM
|IBM
|{{?}}
|MOS
|25&nbsp;mm<sup>2</sup>
|<ref>{{cite web |title=The Cutting Edge of IC Technology: The First 294,912-Bit (288K) Dynamic RAM |url=http://smithsonianchips.si.edu/augarten/p66.htm |website=] |publisher=] |access-date=20 June 2019}}</ref>
|-
|rowspan="2" | 1983
|rowspan="2" | {{?}}
|64 kbit
|DRAM
|Intel
|]
|]
|20&nbsp;mm<sup>2</sup>
|rowspan="2" | <ref name="Gealow"/>
|-
|256 kbit
|DRAM
|NTT
|{{?}}
|CMOS
|31&nbsp;mm<sup>2</sup>
|-
|{{sort|1984|January 5, 1984}}
|{{?}}
|8 ]
|DRAM
|]
|{{?}}
|MOS
|{{?}}
|<ref>{{cite web |title=Computer History for 1984 |url=https://www.computerhope.com/history/1984.htm |website=Computer Hope |access-date=25 June 2019}}</ref><ref>{{cite journal |title=Japanese Technical Abstracts |journal=Japanese Technical Abstracts |date=1987 |volume=2 |issue=3–4 |page=161 |url=https://books.google.com/books?id=Fa0kAQAAIAAJ |publisher=University Microfilms |quote=The announcement of 1M DRAM in 1984 began the era of megabytes.}}</ref>
|-
| rowspan="2" |{{sort|1984|February 1984}}
| rowspan="2" |{{?}}
| rowspan="2" |1 Mbit
| rowspan="2" |DRAM
|Hitachi, NEC
|]
|NMOS
|74{{ndash}}76&nbsp;mm<sup>2</sup>
|<ref name="Gealow"/><ref name="Robinson">{{cite journal |last1=Robinson |first1=Arthur L. |title=Experimental Memory Chips Reach 1 Megabit: As they become larger, memories become an increasingly important part of the integrated circuit business, technologically and economically |journal=] |date=11 May 1984 |volume=224 |issue=4649 |pages=590–592 |doi=10.1126/science.224.4649.590 |pmid=17838349 |issn=0036-8075}}</ref>
|-
|NTT
|]
|CMOS
|53&nbsp;mm<sup>2</sup>
|<ref name="Gealow"/><ref name="Robinson"/>
|-
|1984
|TMS4161
|64 kbit
|] (])
|]
|{{?}}
|NMOS
|{{?}}
|<ref name="ti1984">{{cite book |title=MOS Memory Data Book |url=http://bitsavers.trailing-edge.com/components/ti/_dataBooks/1984_TI_MOS_Memory_Data_Book.pdf |publisher=] |year=1984 |pages=4–15 |access-date=21 June 2019}}</ref><ref>{{cite web |title=Famous Graphics Chips: TI TMS34010 and VRAM |url=https://www.computer.org/publications/tech-news/chasing-pixels/Famous-Graphics-Chips-IBMs-professional-graphics-the-PGC-and-8514A/Famous-Graphics-Chips-TI-TMS34010-and-VRAM |website=] |date=10 January 2019 |access-date=29 June 2019}}</ref>
|-
|{{sort|1985|January 1985}}
|μPD41264
|256 kbit
|DPRAM (VRAM)
|NEC
|{{?}}
|NMOS
|{{?}}
|<ref>{{cite web |title=μPD41264 256K Dual Port Graphics Buffer |url=https://console5.com/techwiki/images/4/4b/UPD41264.pdf |publisher=] |access-date=21 June 2019}}</ref><ref>{{cite web |title=Sense amplifier circuit for switching plural inputs at low power |url=https://patents.google.com/patent/US4808857 |website=] |access-date=21 June 2019}}</ref>
|-
|{{sort|1986|June 1986}}
|{{?}}
|1 Mbit
|PSRAM
|Toshiba
|{{?}}
|CMOS
|{{?}}
|<ref>{{cite journal |title=Fine CMOS techniques create 1M VSRAM |journal=Japanese Technical Abstracts |date=1987 |volume=2 |issue=3–4 |page=161 |url=https://books.google.com/books?id=Fa0kAQAAIAAJ |publisher=University Microfilms}}</ref>
|-
|rowspan="2" | 1986
|rowspan="2" | {{?}}
|rowspan="2" | 4 Mbit
|rowspan="2" | DRAM
|NEC
|800&nbsp;nm
|NMOS
|99&nbsp;mm<sup>2</sup>
|rowspan="2" | <ref name="Gealow"/>
|-
|Texas Instruments, Toshiba
|1,000&nbsp;nm
|CMOS
|100{{ndash}}137&nbsp;mm<sup>2</sup>
|-
|1987
|{{?}}
|16 Mbit
|DRAM
|NTT
|700&nbsp;nm
|CMOS
|148&nbsp;mm<sup>2</sup>
|<ref name="Gealow"/>
|-
|{{sort|1987|October 1988}}
|{{?}}
|512 kbit
|HSDRAM
|IBM
|1,000&nbsp;nm
|CMOS
|78&nbsp;mm<sup>2</sup>
|<ref>{{cite journal |last1=Hanafi |first1=Hussein I. |last2=Lu |first2=Nicky C. C. |last3=Chao |first3=H. H. |last4=Hwang |first4=Wei |last5=Henkels |first5=W. H. |last6=Rajeevakumar |first6=T. V. |last7=Terman |first7=L. M. |last8=Franch |first8=Robert L. |title=A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate |journal=] |date=October 1988 |volume=23 |issue=5 |pages=1140–1149 |doi=10.1109/4.5936|bibcode=1988IJSSC..23.1140L }}</ref>
|-
|1991
|{{?}}
|64 Mbit
|DRAM
|], ], ], Toshiba
|400&nbsp;nm
|CMOS
|{{?}}
| rowspan="2" |<ref name="stol">{{cite web|url=http://maltiel-consulting.com/Semiconductor_technology_memory.html|title=Memory|website=STOL (Semiconductor Technology Online)|access-date=25 June 2019}}</ref>
|-
|1993
|{{?}}
|256 Mbit
|DRAM
|Hitachi, NEC
|]
|CMOS
|{{?}}
|-
|1995
|{{?}}
|4 Mbit
|DPRAM (VRAM)
|Hitachi
|{{?}}
|CMOS
|{{?}}
|<ref name="smithsonian-japan">{{cite web |title=Japanese Company Profiles |url=http://smithsonianchips.si.edu/ice/cd/PROF96/JAPAN.PDF |publisher=] |year=1996 |access-date=27 June 2019}}</ref>
|-
| rowspan="2" |{{sort|1995|January 9, 1995}}
| rowspan="2" |{{?}}
| rowspan="2" |1 ]
| rowspan="2" |DRAM
|NEC
|250&nbsp;nm
|CMOS
|{{?}}
|rowspan="2" |<ref name="HB19950109">, January 9, 1995</ref><ref name="smithsonian-japan"/>
|-
|Hitachi
|160&nbsp;nm
|CMOS
|{{?}}
|-
|1996
|{{?}}
|4 Mbit
|]
|]
|{{?}}
|NMOS
|{{?}}
|<ref>{{cite book |last1=Scott |first1=J.F. |chapter=Nano-Ferroelectrics |editor-last1=Tsakalakos |editor-first1=Thomas |editor-last2=Ovid'ko |editor-first2=Ilya A. |editor-last3=Vasudevan |editor-first3=Asuri K. |title=Nanostructures: Synthesis, Functional Properties and Application |date=2003 |publisher=] |isbn=9789400710191 |pages=584–600 (597) |chapter-url=https://books.google.com/books?id=z2ryCAAAQBAJ&pg=PA597}}</ref>
|-
|1997
|{{?}}
|4 Gbit
|]
|NEC
|150&nbsp;nm
|CMOS
|{{?}}
|<ref name="stol"/>
|-
|1998
|{{?}}
|4 Gbit
|DRAM
|Hyundai
|{{?}}
|CMOS
|{{?}}
|<ref name="hynix90s-skhynix.com"/>
|-
|{{sort|2001|June 2001}}
|TC51W3216XB
|32 Mbit
|PSRAM
|]
|{{?}}
|CMOS
|{{?}}
|<ref>{{cite news |title=Toshiba's new 32 Mb Pseudo-SRAM is no fake |url=https://www.theengineer.co.uk/toshibas-new-32-mb-pseudo-sram-is-no-fake/ |access-date=29 June 2019 |work=The Engineer |date=24 June 2001 |language=en-UK |archive-date=29 June 2019 |archive-url=https://web.archive.org/web/20190629232051/https://www.theengineer.co.uk/toshibas-new-32-mb-pseudo-sram-is-no-fake/ |url-status=dead }}</ref>
|-
|{{sort|2001|February 2001}}
|{{?}}
|4 Gbit

|DRAM
|Samsung
|]
|CMOS
|{{?}}
|<ref name="stol"/><ref>{{cite web |title=A Study of the DRAM industry |url=https://dspace.mit.edu/bitstream/handle/1721.1/59138/659514510-MIT.pdf |publisher=] |date=8 June 2010 |access-date=29 June 2019}}</ref>
|}

===SDRAM===
{{Transcluded section|Synchronous dynamic random-access memory|part=yes}}
{{trim|{{#section::Synchronous dynamic random-access memory|SDRAM timeline}} }}

==See also==
{{Portal|Technology}}
{{Columns-list|colwidth=30em|
* ] (CL) * ] (CL)
* ] * ]
* ]
* ] (Error-correcting code)
* ] * ]
* ] * ]
* ]
* ]
* ]
* ] (RMM)
* ]
}}


==References==
== Notes and references ==
{{reflist}} {{reflist|30em}}


==External links== ==External links==
* {{Commons-inline|RAM}}

{{Basic computer components}}

{{Authority control}}


{{DEFAULTSORT:Random-Access Memory}} {{DEFAULTSORT:Random-Access Memory}}
]
]
] ]
]

]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]

Latest revision as of 23:51, 16 January 2025

Form of computer data storage "RAM" redirects here. For other uses, see RAM (disambiguation). Not to be confused with Random Access Memories or Random-access machine.

Example of writable volatile random-access memory: Synchronous dynamic RAM modules, primarily used as main memory in personal computers, workstations, and servers.
Computer memory and data storage types
General
Volatile
RAM
Historical
Non-volatile
ROM
NVRAM
Early-stage NVRAM
Analog recording
Optical
In development
Historical
A 64 bit memory chip die, the SP95 Phase 2 buffer memory produced at IBM mid-1960s, versus memory core iron rings
8GB DDR3 RAM stick with a white heatsink

Random-access memory (RAM; /ræm/) is a form of electronic computer memory that can be read and changed in any order, typically used to store working data and machine code. A random-access memory device allows data items to be read or written in almost the same amount of time irrespective of the physical location of data inside the memory, in contrast with other direct-access data storage media (such as hard disks and magnetic tape), where the time required to read and write data items varies significantly depending on their physical locations on the recording medium, due to mechanical limitations such as media rotation speeds and arm movement.

In today's technology, random-access memory takes the form of integrated circuit (IC) chips with MOS (metal–oxide–semiconductor) memory cells. RAM is normally associated with volatile types of memory where stored information is lost if power is removed. The two main types of volatile random-access semiconductor memory are static random-access memory (SRAM) and dynamic random-access memory (DRAM).

Non-volatile RAM has also been developed and other types of non-volatile memories allow random access for read operations, but either do not allow write operations or have other kinds of limitations. These include most types of ROM and NOR flash memory.

The use of semiconductor RAM dates back to 1965 when IBM introduced the monolithic (single-chip) 16-bit SP95 SRAM chip for their System/360 Model 95 computer, and Toshiba used bipolar DRAM memory cells for its 180-bit Toscal BC-1411 electronic calculator, both based on bipolar transistors. While it offered higher speeds than magnetic-core memory, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory. In 1966, Dr. Robert Dennard invented modern DRAM architecture in which there's a single MOS transistor per capacitor. The first commercial DRAM IC chip, the 1K Intel 1103, was introduced in October 1970. Synchronous dynamic random-access memory (SDRAM) was reintroduced with the Samsung KM48SL2000 chip in 1992.

History

These IBM tabulating machines from the mid-1930s used mechanical counters to store information.

Early computers used relays, mechanical counters or delay lines for main memory functions. Ultrasonic delay lines were serial devices which could only reproduce data in the order it was written. Drum memory could be expanded at relatively low cost but efficient retrieval of memory items requires knowledge of the physical layout of the drum to optimize speed. Latches built out of triode vacuum tubes, and later, out of discrete transistors, were used for smaller and faster memories such as registers. Such registers were relatively large and too costly to use for large amounts of data; generally only a few dozen or few hundred bits of such memory could be provided.

The first practical form of random-access memory was the Williams tube. It stored data as electrically charged spots on the face of a cathode-ray tube. Since the electron beam of the CRT could read and write the spots on the tube in any order, memory was random access. The capacity of the Williams tube was a few hundred to around a thousand bits, but it was much smaller, faster, and more power-efficient than using individual vacuum tube latches. Developed at the University of Manchester in England, the Williams tube provided the medium on which the first electronically stored program was implemented in the Manchester Baby computer, which first successfully ran a program on 21 June, 1948. In fact, rather than the Williams tube memory being designed for the Baby, the Baby was a testbed to demonstrate the reliability of the memory.

Magnetic-core memory was invented in 1947 and developed up until the mid-1970s. It became a widespread form of random-access memory, relying on an array of magnetized rings. By changing the sense of each ring's magnetization, data could be stored with one bit stored per ring. Since every ring had a combination of address wires to select and read or write it, access to any memory location in any sequence was possible. Magnetic core memory was the standard form of computer memory until displaced by semiconductor memory in integrated circuits (ICs) during the early 1970s.

Prior to the development of integrated read-only memory (ROM) circuits, permanent (or read-only) random-access memory was often constructed using diode matrices driven by address decoders, or specially wound core rope memory planes.

Semiconductor memory appeared in the 1960s with bipolar memory, which used bipolar transistors. Although it was faster, it could not compete with the lower price of magnetic core memory.

MOS RAM

In 1957, Frosch and Derick manufactured the first silicon dioxide field-effect transistors at Bell Labs, the first transistors in which drain and source were adjacent at the surface. Subsequently, in 1960, a team demonstrated a working MOSFET at Bell Labs. This led to the development of metal–oxide–semiconductor (MOS) memory by John Schmidt at Fairchild Semiconductor in 1964. In addition to higher speeds, MOS semiconductor memory was cheaper and consumed less power than magnetic core memory. The development of silicon-gate MOS integrated circuit (MOS IC) technology by Federico Faggin at Fairchild in 1968 enabled the production of MOS memory chips. MOS memory overtook magnetic core memory as the dominant memory technology in the early 1970s.

Integrated bipolar static random-access memory (SRAM) was invented by Robert H. Norman at Fairchild Semiconductor in 1963. It was followed by the development of MOS SRAM by John Schmidt at Fairchild in 1964. SRAM became an alternative to magnetic-core memory, but required six MOS transistors for each bit of data. Commercial use of SRAM began in 1965, when IBM introduced the SP95 memory chip for the System/360 Model 95.

Dynamic random-access memory (DRAM) allowed replacement of a 4 or 6-transistor latch circuit by a single transistor for each memory bit, greatly increasing memory density at the cost of volatility. Data was stored in the tiny capacitance of each transistor and had to be periodically refreshed every few milliseconds before the charge could leak away.

Toshiba's Toscal BC-1411 electronic calculator, which was introduced in 1965, used a form of capacitor bipolar DRAM, storing 180-bit data on discrete memory cells, consisting of germanium bipolar transistors and capacitors. Capacitors had also been used for earlier memory schemes, such as the drum of the Atanasoff–Berry Computer, the Williams tube and the Selectron tube. While it offered higher speeds than magnetic-core memory, bipolar DRAM could not compete with the lower price of the then-dominant magnetic-core memory.

CMOS 1-megabit (Mbit) DRAM chip, one of the last models developed by VEB Carl Zeiss Jena, in 1989

In 1966, Robert Dennard invented modern DRAM architecture for which there is a single MOS transistor per capacitor. While examining the characteristics of MOS technology, he found it was capable of building capacitors, and that storing a charge or no charge on the MOS capacitor could represent the 1 and 0 of a bit, while the MOS transistor could control writing the charge to the capacitor. This led to his development of a single-transistor DRAM memory cell. In 1967, Dennard filed a patent under IBM for a single-transistor DRAM memory cell, based on MOS technology. The first commercial DRAM IC chip was the Intel 1103, which was manufactured on an 8 μm MOS process with a capacity of 1 kbit, and was released in 1970.

The earliest DRAMs were often synchronized with the CPU clock (clocked) and were used with early microprocessors. In the mid-1970s, DRAMs moved to the asynchronous design, but in the 1990s returned to synchronous operation. In 1992 Samsung released KM48SL2000, which had a capacity of 16 Mbit. and mass-produced in 1993. The first commercial DDR SDRAM (double data rate SDRAM) memory chip was Samsung's 64 Mbit DDR SDRAM chip, released in June 1998. GDDR (graphics DDR) is a form of DDR SGRAM (synchronous graphics RAM), which was first released by Samsung as a 16 Mbit memory chip in 1998.

Types

The two widely used forms of modern RAM are static RAM (SRAM) and dynamic RAM (DRAM). In SRAM, a bit of data is stored using the state of a six-transistor memory cell, typically using six MOSFETs. This form of RAM is more expensive to produce, but is generally faster and requires less dynamic power than DRAM. In modern computers, SRAM is often used as cache memory for the CPU. DRAM stores a bit of data using a transistor and capacitor pair (typically a MOSFET and MOS capacitor, respectively), which together comprise a DRAM cell. The capacitor holds a high or low charge (1 or 0, respectively), and the transistor acts as a switch that lets the control circuitry on the chip read the capacitor's state of charge or change it. As this form of memory is less expensive to produce than static RAM, it is the predominant form of computer memory used in modern computers.

Both static and dynamic RAM are considered volatile, as their state is lost or reset when power is removed from the system. By contrast, read-only memory (ROM) stores data by permanently enabling or disabling selected transistors, such that the memory cannot be altered. Writable variants of ROM (such as EEPROM and NOR flash) share properties of both ROM and RAM, enabling data to persist without power and to be updated without requiring special equipment. ECC memory (which can be either SRAM or DRAM) includes special circuitry to detect and/or correct random faults (memory errors) in the stored data, using parity bits or error correction codes.

In general, the term RAM refers solely to solid-state memory devices (either DRAM or SRAM), and more specifically the main memory in most computers. In optical storage, the term DVD-RAM is somewhat of a misnomer since, it is not random access; it behaves much like a hard disc drive if somewhat slower. Aside, unlike CD-RW or DVD-RW, DVD-RAM does not need to be erased before reuse.

Memory cell

Main article: Memory cell (computing)

The memory cell is the fundamental building block of computer memory. The memory cell is an electronic circuit that stores one bit of binary information and it must be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained/stored until it is changed by the set/reset process. The value in the memory cell can be accessed by reading it.

In SRAM, the memory cell is a type of flip-flop circuit, usually implemented using FETs. This means that SRAM requires very low power when not being accessed, but it is expensive and has low storage density.

A second type, DRAM, is based around a capacitor. Charging and discharging this capacitor can store a "1" or a "0" in the cell. However, the charge in this capacitor slowly leaks away, and must be refreshed periodically. Because of this refresh process, DRAM uses more power, but it can achieve greater storage densities and lower unit costs compared to SRAM.

SRAM cell (6 transistors)
DRAM cell (1 transistor and one capacitor)

Addressing

To be useful, memory cells must be readable and writable. Within the RAM device, multiplexing and demultiplexing circuitry is used to select memory cells. Typically, a RAM device has a set of address lines A 0 , A 1 , . . . A n {\displaystyle A_{0},A_{1},...A_{n}} , and for each combination of bits that may be applied to these lines, a set of memory cells are activated. Due to this addressing, RAM devices virtually always have a memory capacity that is a power of two.

Usually several memory cells share the same address. For example, a 4 bit "wide" RAM chip has four memory cells for each address. Often the width of the memory and that of the microprocessor are different, for a 32 bit microprocessor, eight 4 bit RAM chips would be needed.

Often more addresses are needed than can be provided by a device. In that case, external multiplexors to the device are used to activate the correct device that is being accessed. RAM is often byte addressable, although it is also possible to make RAM that is word-addressable.

Memory hierarchy

Main article: Memory hierarchy

One can read and over-write data in RAM. Many computer systems have a memory hierarchy consisting of processor registers, on-die SRAM caches, external caches, DRAM, paging systems and virtual memory or swap space on a hard drive. This entire pool of memory may be referred to as "RAM" by many developers, even though the various subsystems can have very different access times, violating the original concept behind the random access term in RAM. Even within a hierarchy level such as DRAM, the specific row, column, bank, rank, channel, or interleave organization of the components make the access time variable, although not to the extent that access time to rotating storage media or a tape is variable. The overall goal of using a memory hierarchy is to obtain the fastest possible average access time while minimizing the total cost of the entire memory system (generally, the memory hierarchy follows the access time with the fast CPU registers at the top and the slow hard drive at the bottom).

In many modern personal computers, the RAM comes in an easily upgraded form of modules called memory modules or DRAM modules about the size of a few sticks of chewing gum. These can be quickly replaced should they become damaged or when changing needs demand more storage capacity. As suggested above, smaller amounts of RAM (mostly SRAM) are also integrated in the CPU and other ICs on the motherboard, as well as in hard-drives, CD-ROMs, and several other parts of the computer system.

Other uses of RAM

A SO-DIMM stick of laptop RAM, roughly half the size of desktop RAM

In addition to serving as temporary storage and working space for the operating system and applications, RAM is used in numerous other ways.

Virtual memory

Main article: Virtual memory

Most modern operating systems employ a method of extending RAM capacity, known as "virtual memory". A portion of the computer's hard drive is set aside for a paging file or a scratch partition, and the combination of physical RAM and the paging file form the system's total memory. (For example, if a computer has 2 GB (1024 B) of RAM and a 1 GB page file, the operating system has 3 GB total memory available to it.) When the system runs low on physical memory, it can "swap" portions of RAM to the paging file to make room for new data, as well as to read previously swapped information back into RAM. Excessive use of this mechanism results in thrashing and generally hampers overall system performance, mainly because hard drives are far slower than RAM.

RAM disk

Main article: RAM drive

Software can "partition" a portion of a computer's RAM, allowing it to act as a much faster hard drive that is called a RAM disk. A RAM disk loses the stored data when the computer is shut down, unless memory is arranged to have a standby battery source, or changes to the RAM disk are written out to a nonvolatile disk. The RAM disk is reloaded from the physical disk upon RAM disk initialization.

Shadow RAM

Sometimes, the contents of a relatively slow ROM chip are copied to read/write memory to allow for shorter access times. The ROM chip is then disabled while the initialized memory locations are switched in on the same block of addresses (often write-protected). This process, sometimes called shadowing, is fairly common in both computers and embedded systems.

As a common example, the BIOS in typical personal computers often has an option called "use shadow BIOS" or similar. When enabled, functions that rely on data from the BIOS's ROM instead use DRAM locations (most can also toggle shadowing of video card ROM or other ROM sections). Depending on the system, this may not result in increased performance, and may cause incompatibilities. For example, some hardware may be inaccessible to the operating system if shadow RAM is used. On some systems the benefit may be hypothetical because the BIOS is not used after booting in favor of direct hardware access. Free memory is reduced by the size of the shadowed ROMs.

Memory wall

The 'memory wall is the growing disparity of speed between CPU and the response time of memory (known as memory latency) outside the CPU chip. An important reason for this disparity is the limited communication bandwidth beyond chip boundaries, which is also referred to as bandwidth wall. From 1986 to 2000, CPU speed improved at an annual rate of 55% while off-chip memory response time only improved at 10%. Given these trends, it was expected that memory latency would become an overwhelming bottleneck in computer performance.

Another reason for the disparity is the enormous increase in the size of memory since the start of the PC revolution in the 1980s. Originally, PCs contained less than 1 mebibyte of RAM, which often had a response time of 1 CPU clock cycle, meaning that it required 0 wait states. Larger memory units are inherently slower than smaller ones of the same type, simply because it takes longer for signals to traverse a larger circuit. Constructing a memory unit of many gibibytes with a response time of one clock cycle is difficult or impossible. Today's CPUs often still have a mebibyte of 0 wait state cache memory, but it resides on the same chip as the CPU cores due to the bandwidth limitations of chip-to-chip communication. It must also be constructed from static RAM, which is far more expensive than the dynamic RAM used for larger memories. Static RAM also consumes far more power.

CPU speed improvements slowed significantly partly due to major physical barriers and partly because current CPU designs have already hit the memory wall in some sense. Intel summarized these causes in a 2005 document.

First of all, as chip geometries shrink and clock frequencies rise, the transistor leakage current increases, leading to excess power consumption and heat... Secondly, the advantages of higher clock speeds are in part negated by memory latency, since memory access times have not been able to keep pace with increasing clock frequencies. Third, for certain applications, traditional serial architectures are becoming less efficient as processors get faster (due to the so-called von Neumann bottleneck), further undercutting any gains that frequency increases might otherwise buy. In addition, partly due to limitations in the means of producing inductance within solid state devices, resistance-capacitance (RC) delays in signal transmission are growing as feature sizes shrink, imposing an additional bottleneck that frequency increases don't address.

The RC delays in signal transmission were also noted in "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures" which projected a maximum of 12.5% average annual CPU performance improvement between 2000 and 2014.

A different concept is the processor-memory performance gap, which can be addressed by 3D integrated circuits that reduce the distance between the logic and memory aspects that are further apart in a 2D chip. Memory subsystem design requires a focus on the gap, which is widening over time. The main method of bridging the gap is the use of caches; small amounts of high-speed memory that houses recent operations and instructions nearby the processor, speeding up the execution of those operations or instructions in cases where they are called upon frequently. Multiple levels of caching have been developed to deal with the widening gap, and the performance of high-speed modern computers relies on evolving caching techniques. There can be up to a 53% difference between the growth in speed of processor and the lagging speed of main memory access.

Solid-state hard drives have continued to increase in speed, from ~400 Mbit/s via SATA3 in 2012 up to ~7 GB/s via NVMe/PCIe in 2024, closing the gap between RAM and hard disk speeds, although RAM continues to be an order of magnitude faster, with single-lane DDR5 8000MHz capable of 128 GB/s, and modern GDDR even faster. Fast, cheap, non-volatile solid state drives have replaced some functions formerly performed by RAM, such as holding certain data for immediate availability in server farms - 1 terabyte of SSD storage can be had for $200, while 1 TB of RAM would cost thousands of dollars.

Timeline

See also: Flash memory § Timeline, Read-only memory § Timeline, and Transistor count § Memory

SRAM

Static random-access memory (SRAM)
Date of introduction Chip name Capacity (bits) Access time SRAM type Manufacturer(s) Process MOSFET Ref
March 1963 1 ? Bipolar (cell) Fairchild
1965 ? 8 ? Bipolar IBM ?
SP95 16 ? Bipolar IBM ?
? 64 ? MOSFET Fairchild ? PMOS
1966 TMC3162 16 ? Bipolar (TTL) Transitron ?
? ? ? MOSFET NEC ? ?
1968 ? 64 ? MOSFET Fairchild ? PMOS
144 ? MOSFET NEC ? NMOS
512 ? MOSFET IBM ? NMOS
1969 ? 128 ? Bipolar IBM ?
1101 256 850 ns MOSFET Intel 12,000 nm PMOS
1972 2102 1 kbit ? MOSFET Intel ? NMOS
1974 5101 1 kbit 800 ns MOSFET Intel ? CMOS
2102A 1 kbit 350 ns MOSFET Intel ? NMOS (depletion)
1975 2114 4 kbit 450 ns MOSFET Intel ? NMOS
1976 2115 1 kbit 70 ns MOSFET Intel ? NMOS (HMOS)
2147 4 kbit 55 ns MOSFET Intel ? NMOS (HMOS)
1977 ? 4 kbit ? MOSFET Toshiba ? CMOS
1978 HM6147 4 kbit 55 ns MOSFET Hitachi 3,000 nm CMOS (twin-well)
TMS4016 16 kbit ? MOSFET Texas Instruments ? NMOS
1980 ? 16 kbit ? MOSFET Hitachi, Toshiba ? CMOS
64 kbit ? MOSFET Matsushita
1981 ? 16 kbit ? MOSFET Texas Instruments 2,500 nm NMOS
October 1981 ? 4 kbit 18 ns MOSFET Matsushita, Toshiba 2,000 nm CMOS
1982 ? 64 kbit ? MOSFET Intel 1,500 nm NMOS (HMOS)
February 1983 ? 64 kbit 50 ns MOSFET Mitsubishi ? CMOS
1984 ? 256 kbit ? MOSFET Toshiba 1,200 nm CMOS
1987 ? 1 Mbit ? MOSFET Sony, Hitachi, Mitsubishi, Toshiba ? CMOS
December 1987 ? 256 kbit 10 ns BiMOS Texas Instruments 800 nm BiCMOS
1990 ? 4 Mbit 15–23 ns MOSFET NEC, Toshiba, Hitachi, Mitsubishi ? CMOS
1992 ? 16 Mbit 12–15 ns MOSFET Fujitsu, NEC 400 nm
December 1994 ? 512 kbit 2.5 ns MOSFET IBM ? CMOS (SOI)
1995 ? 4 Mbit 6 ns Cache (SyncBurst) Hitachi 100 nm CMOS
256 Mbit ? MOSFET Hyundai ? CMOS

DRAM

Dynamic random-access memory (DRAM)
Date of introduction Chip name Capacity (bits) DRAM type Manufacturer(s) Process MOSFET Area Ref
1965 1 bit DRAM (cell) Toshiba
1967 1 bit DRAM (cell) IBM MOS
1968 ? 256 bit DRAM (IC) Fairchild ? PMOS ?
1969 1 bit DRAM (cell) Intel PMOS
1970 1102 1 kbit DRAM (IC) Intel, Honeywell ? PMOS ?
1103 1 kbit DRAM Intel 8,000 nm PMOS 10 mm
1971 μPD403 1 kbit DRAM NEC ? NMOS ?
? 2 kbit DRAM General Instrument ? PMOS 13 mm
1972 2107 4 kbit DRAM Intel ? NMOS ?
1973 ? 8 kbit DRAM IBM ? PMOS 19 mm
1975 2116 16 kbit DRAM Intel ? NMOS ?
1977 ? 64 kbit DRAM NTT ? NMOS 35 mm
1979 MK4816 16 kbit PSRAM Mostek ? NMOS ?
? 64 kbit DRAM Siemens ? VMOS 25 mm
1980 ? 256 kbit DRAM NEC, NTT 1,000–1,500 nm NMOS 34–42 mm
1981 ? 288 kbit DRAM IBM ? MOS 25 mm
1983 ? 64 kbit DRAM Intel 1,500 nm CMOS 20 mm
256 kbit DRAM NTT ? CMOS 31 mm
January 5, 1984 ? 8 Mbit DRAM Hitachi ? MOS ?
February 1984 ? 1 Mbit DRAM Hitachi, NEC 1,000 nm NMOS 74–76 mm
NTT 800 nm CMOS 53 mm
1984 TMS4161 64 kbit DPRAM (VRAM) Texas Instruments ? NMOS ?
January 1985 μPD41264 256 kbit DPRAM (VRAM) NEC ? NMOS ?
June 1986 ? 1 Mbit PSRAM Toshiba ? CMOS ?
1986 ? 4 Mbit DRAM NEC 800 nm NMOS 99 mm
Texas Instruments, Toshiba 1,000 nm CMOS 100–137 mm
1987 ? 16 Mbit DRAM NTT 700 nm CMOS 148 mm
October 1988 ? 512 kbit HSDRAM IBM 1,000 nm CMOS 78 mm
1991 ? 64 Mbit DRAM Matsushita, Mitsubishi, Fujitsu, Toshiba 400 nm CMOS ?
1993 ? 256 Mbit DRAM Hitachi, NEC 250 nm CMOS ?
1995 ? 4 Mbit DPRAM (VRAM) Hitachi ? CMOS ?
January 9, 1995 ? 1 Gbit DRAM NEC 250 nm CMOS ?
Hitachi 160 nm CMOS ?
1996 ? 4 Mbit FRAM Samsung ? NMOS ?
1997 ? 4 Gbit QLC NEC 150 nm CMOS ?
1998 ? 4 Gbit DRAM Hyundai ? CMOS ?
June 2001 TC51W3216XB 32 Mbit PSRAM Toshiba ? CMOS ?
February 2001 ? 4 Gbit DRAM Samsung 100 nm CMOS ?

SDRAM

Part of this section is transcluded from Synchronous dynamic random-access memory. (edit | history)
Synchronous dynamic random-access memory (SDRAM)
Date of introduction Chip name Capacity (bits) SDRAM type Manufacturer(s) Process MOSFET Area Ref
1992 KM48SL2000 16 Mbit SDR Samsung ? CMOS ?
1996 MSM5718C50 18 Mbit RDRAM Oki ? CMOS 325 mm
N64 RDRAM 36 Mbit RDRAM NEC ? CMOS ?
? 1024 Mbit SDR Mitsubishi 150 nm CMOS ?
1997 ? 1024 Mbit SDR Hyundai ? SOI ?
1998 MD5764802 64 Mbit RDRAM Oki ? CMOS 325 mm
March 1998 Direct RDRAM 72 Mbit RDRAM Rambus ? CMOS ?
June 1998 ? 64 Mbit DDR Samsung ? CMOS ?
1998 ? 64 Mbit DDR Hyundai ? CMOS ?
128 Mbit SDR Samsung ? CMOS ?
1999 ? 128 Mbit DDR Samsung ? CMOS ?
1024 Mbit DDR Samsung 140 nm CMOS ?
2000 GS eDRAM 32 Mbit eDRAM Sony, Toshiba 180 nm CMOS 279 mm
2001 ? 288 Mbit RDRAM Hynix ? CMOS ?
? DDR2 Samsung 100 nm CMOS ?
2002 ? 256 Mbit SDR Hynix ? CMOS ?
2003 EE+GS eDRAM 32 Mbit eDRAM Sony, Toshiba 90 nm CMOS 86 mm
? 72 Mbit DDR3 Samsung 90 nm CMOS ?
512 Mbit DDR2 Hynix ? CMOS ?
Elpida 110 nm CMOS ?
1024 Mbit DDR2 Hynix ? CMOS ?
2004 ? 2048 Mbit DDR2 Samsung 80 nm CMOS ?
2005 EE+GS eDRAM 32 Mbit eDRAM Sony, Toshiba 65 nm CMOS 86 mm
Xenos eDRAM 80 Mbit eDRAM NEC 90 nm CMOS ?
? 512 Mbit DDR3 Samsung 80 nm CMOS ?
2006 ? 1024 Mbit DDR2 Hynix 60 nm CMOS ?
2008 ? ? LPDDR2 Hynix ?
April 2008 ? 8192 Mbit DDR3 Samsung 50 nm CMOS ?
2008 ? 16384 Mbit DDR3 Samsung 50 nm CMOS ?
2009 ? ? DDR3 Hynix 44 nm CMOS ?
2048 Mbit DDR3 Hynix 40 nm
2011 ? 16384 Mbit DDR3 Hynix 40 nm CMOS ?
2048 Mbit DDR4 Hynix 30 nm CMOS ?
2013 ? ? LPDDR4 Samsung 20 nm CMOS ?
2014 ? 8192 Mbit LPDDR4 Samsung 20 nm CMOS ?
2015 ? 12 Gbit LPDDR4 Samsung 20 nm CMOS ?
2018 ? 8192 Mbit LPDDR5 Samsung 10 nm FinFET ?
128 Gbit DDR4 Samsung 10 nm FinFET ?

SGRAM and HBM

Synchronous graphics random-access memory (SGRAM) and High Bandwidth Memory (HBM)
Date of introduction Chip name Capacity (bits) SDRAM type Manufacturer(s) Process MOSFET Area Ref
November 1994 HM5283206 8 Mbit SGRAM (SDR) Hitachi 350 nm CMOS 58 mm
December 1994 μPD481850 8 Mbit SGRAM (SDR) NEC ? CMOS 280 mm
1997 μPD4811650 16 Mbit SGRAM (SDR) NEC 350 nm CMOS 280 mm
September 1998 ? 16 Mbit SGRAM (GDDR) Samsung ? CMOS ?
1999 KM4132G112 32 Mbit SGRAM (SDR) Samsung ? CMOS 280 mm
2002 ? 128 Mbit SGRAM (GDDR2) Samsung ? CMOS ?
2003 ? 256 Mbit SGRAM (GDDR2) Samsung ? CMOS ?
SGRAM (GDDR3)
March 2005 K4D553238F 256 Mbit SGRAM (GDDR) Samsung ? CMOS 77 mm
October 2005 ? 256 Mbit SGRAM (GDDR4) Samsung ? CMOS ?
2005 ? 512 Mbit SGRAM (GDDR4) Hynix ? CMOS ?
2007 ? 1024 Mbit SGRAM (GDDR5) Hynix 60 nm
2009 ? 2048 Mbit SGRAM (GDDR5) Hynix 40 nm
2010 K4W1G1646G 1024 Mbit SGRAM (GDDR3) Samsung ? CMOS 100 mm
2012 ? 4096 Mbit SGRAM (GDDR3) SK Hynix ? CMOS ?
2013 ? ? HBM
March 2016 MT58K256M32JA 8 Gbit SGRAM (GDDR5X) Micron 20 nm CMOS 140 mm
June 2016 ? 32 Gbit HBM2 Samsung 20 nm CMOS ?
2017 ? 64 Gbit HBM2 Samsung 20 nm CMOS ?
January 2018 K4ZAF325BM 16 Gbit SGRAM (GDDR6) Samsung 10 nm FinFET 225 mm

See also

References

  1. "RAM". Cambridge English Dictionary. Retrieved 11 July 2019.
  2. "RAM". Oxford Advanced Learner's Dictionary. Retrieved 11 July 2019.
  3. Gallagher, Sean (April 4, 2013). "Memory that never forgets: non-volatile DIMMs hit the market". Ars Technica. Archived from the original on July 8, 2017.
  4. "1966: Semiconductor RAMs Serve High-speed Storage Needs". Computer History Museum.
  5. US3387286A, Dennard, Robert H., "Field-effect transistor memory", issued 1968-06-04 
  6. "IBM Archives -- FAQ's for Products and Services". ibm.com. Archived from the original on 2012-10-23.
  7. Napper, Brian, Computer 50: The University of Manchester Celebrates the Birth of the Modern Computer, archived from the original on 4 May 2012, retrieved 26 May 2012
  8. Williams, F. C.; Kilburn, T. (Sep 1948), "Electronic Digital Computers", Nature, 162 (4117): 487, Bibcode:1948Natur.162..487W, doi:10.1038/162487a0, S2CID 4110351. Reprinted in The Origins of Digital Computers.
  9. Williams, F. C.; Kilburn, T.; Tootill, G. C. (Feb 1951), "Universal High-Speed Digital Computers: A Small-Scale Experimental Machine", Proc. IEE, 98 (61): 13–28, doi:10.1049/pi-2.1951.0004, archived from the original on 2013-11-17.
  10. ^ "1970: Semiconductors compete with magnetic cores". Computer History Museum. Retrieved 19 June 2019.
  11. ^ "1966: Semiconductor RAMs Serve High-speed Storage Needs". Computer History Museum. Retrieved 19 June 2019.
  12. Frosch, C. J.; Derick, L (1957). "Surface Protection and Selective Masking during Diffusion in Silicon". Journal of the Electrochemical Society. 104 (9): 547. doi:10.1149/1.2428650.
  13. KAHNG, D. (1961). "Silicon-Silicon Dioxide Surface Device". Technical Memorandum of Bell Laboratories: 583–596. doi:10.1142/9789814503464_0076. ISBN 978-981-02-0209-5.
  14. Lojek, Bo (2007). History of Semiconductor Engineering. Berlin, Heidelberg: Springer-Verlag Berlin Heidelberg. p. 321. ISBN 978-3-540-34258-8.
  15. Solid State Design – Vol. 6. Horizon House. 1965.
  16. "1968: Silicon Gate Technology Developed for ICs". Computer History Museum. Retrieved 10 August 2019.
  17. US patent 3562721, Robert H. Norman, "Solid State Switching and Memory Apparatus", published 9 February 1971 
  18. ^ "DRAM". IBM100. IBM. 9 August 2017. Retrieved 20 September 2019.
  19. Toscal BC-1411 calculator. Archived 2017-07-29 at the Wayback Machine, Science Museum, London.
  20. ^ "Spec Sheet for Toshiba "TOSCAL" BC-1411". Old Calculator Web Museum. Archived from the original on 3 July 2017. Retrieved 8 May 2018.
  21. ^ Toshiba "Toscal" BC-1411 Desktop Calculator Archived 2007-05-20 at the Wayback Machine
  22. "1966: Semiconductor RAMs Serve High-speed Storage Needs". Computer History Museum.
  23. ^ "Robert Dennard". Encyclopedia Britannica. Retrieved 8 July 2019.
  24. ^ Lojek, Bo (2007). History of Semiconductor Engineering. Springer Science & Business Media. pp. 362–363. ISBN 9783540342588. The i1103 was manufactured on a 6-mask silicon-gate P-MOS process with 8 μm minimum features. The resulting product had a 2,400 μm memory cell size, a die size just under 10 mm, and sold for around $21.
  25. Bellis, Mary. "The Invention of the Intel 1103". Archived from the original on 2020-03-14. Retrieved 2015-07-11.
  26. P. Darche (2020). Microprocessor: Prolegomenes - Calculation and Storage Functions - Calculation Models and Computer. John Wiley & Sons. p. 59. ISBN 9781786305633.
  27. B. Jacob; S. W. Ng; D. T. Wang (2008). Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann. p. 324. ISBN 9780080553849.
  28. ^ "Electronic Design". Electronic Design. 41 (15–21). Hayden Publishing Company. 1993. The first commercial synchronous DRAM, the Samsung 16-Mbit KM48SL2000, employs a single-bank architecture that lets system designers easily transition from asynchronous to synchronous systems.
  29. "KM48SL2000-7 Datasheet". Samsung. August 1992. Retrieved 19 June 2019.
  30. "Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option". Samsung Electronics. Samsung. 10 February 1999. Retrieved 23 June 2019.
  31. "Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs". Samsung Electronics. Samsung. 17 September 1998. Retrieved 23 June 2019.
  32. Sze, Simon M. (2002). Semiconductor Devices: Physics and Technology (PDF) (2nd ed.). Wiley. p. 214. ISBN 0-471-33372-7.
  33. The Essentials of Computer Organization and Architecture. Jones & Bartlett Learning. 2006. ISBN 978-0-7637-3769-6.
  34. Anderson, Alexander John (25 October 2020). Foundations of Computer Technology. CRC Press. ISBN 978-1-000-15371-2.
  35. "Shadow Ram". Archived from the original on 2006-10-29. Retrieved 2007-07-24.
  36. The term was coined in "Archived copy" (PDF). Archived (PDF) from the original on 2012-04-06. Retrieved 2011-12-14.{{cite web}}: CS1 maint: archived copy as title (link).
  37. "Platform 2015: Intel Processor and Platform Evolution for the Next Decade" (PDF). March 2, 2005. Archived (PDF) from the original on April 27, 2011.
  38. Agarwal, Vikas; Hrishikesh, M. S.; Keckler, Stephen W.; Burger, Doug (June 10–14, 2000). "Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures" (PDF). Proceedings of the 27th Annual International Symposium on Computer Architecture. 27th Annual International Symposium on Computer Architecture. Vancouver, BC. Retrieved 14 July 2018.
  39. Rainer Waser (2012). Nanoelectronics and Information Technology. John Wiley & Sons. p. 790. ISBN 9783527409273. Archived from the original on August 1, 2016. Retrieved March 31, 2014.
  40. Chris Jesshope and Colin Egan (2006). Advances in Computer Systems Architecture: 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings. Springer. p. 109. ISBN 9783540400561. Archived from the original on August 1, 2016. Retrieved March 31, 2014.
  41. Ahmed Amine Jerraya and Wayne Wolf (2005). Multiprocessor Systems-on-chips. Morgan Kaufmann. pp. 90–91. ISBN 9780123852519. Archived from the original on August 1, 2016. Retrieved March 31, 2014.
  42. Celso C. Ribeiro and Simone L. Martins (2004). Experimental and Efficient Algorithms: Third International Workshop, WEA 2004, Angra Dos Reis, Brazil, May 25-28, 2004, Proceedings, Volume 3. Springer. p. 529. ISBN 9783540220671. Archived from the original on August 1, 2016. Retrieved March 31, 2014.
  43. "SSD Prices Continue to Fall, Now Upgrade Your Hard Drive!". MiniTool. 2018-09-03. Retrieved 2019-03-28.
  44. Coppock, Mark (31 January 2017). "If you're buying or upgrading your PC, expect to pay more for RAM". www.digitaltrends.com. Retrieved 2019-03-28.
  45. IBM first in IC memory. IBM Corporation. 1965. Retrieved 19 June 2019. {{cite book}}: |website= ignored (help)
  46. ^ Sah, Chih-Tang (October 1988). "Evolution of the MOS transistor-from conception to VLSI" (PDF). Proceedings of the IEEE. 76 (10): 1280–1326 (1303). Bibcode:1988IEEEP..76.1280S. doi:10.1109/5.16328. ISSN 0018-9219.
  47. ^ "Late 1960s: Beginnings of MOS memory" (PDF). Semiconductor History Museum of Japan. 2019-01-23. Retrieved 27 June 2019.
  48. ^ "A chronological list of Intel products. The products are sorted by date" (PDF). Intel museum. Intel Corporation. July 2005. Archived from the original (PDF) on August 9, 2007. Retrieved July 31, 2007.
  49. ^ "1970s: SRAM evolution" (PDF). Semiconductor History Museum of Japan. Retrieved 27 June 2019.
  50. ^ Pimbley, J. (2012). Advanced CMOS Process Technology. Elsevier. p. 7. ISBN 9780323156806.
  51. "Intel Memory". Intel Vintage. Archived from the original on 2022-03-19. Retrieved 2019-07-06.
  52. ^ Component Data Catalog (PDF). Intel. 1978. p. 3. Retrieved 27 June 2019.
  53. "Silicon Gate MOS 2102A". Intel. Retrieved 27 June 2019.
  54. ^ "1978: Double-well fast CMOS SRAM (Hitachi)" (PDF). Semiconductor History Museum of Japan. Retrieved 5 July 2019.
  55. ^ "Memory". STOL (Semiconductor Technology Online). Retrieved 25 June 2019.
  56. Isobe, Mitsuo; Uchida, Yukimasa; Maeguchi, Kenji; Mochizuki, T.; Kimura, M.; Hatano, H.; Mizutani, Y.; Tango, H. (October 1981). "An 18 ns CMOS/SOS 4K static RAM". IEEE Journal of Solid-State Circuits. 16 (5): 460–465. Bibcode:1981IJSSC..16..460I. doi:10.1109/JSSC.1981.1051623. S2CID 12992820.
  57. Yoshimoto, M.; Anami, K.; Shinohara, H.; Yoshihara, T.; Takagi, H.; Nagao, S.; Kayano, S.; Nakano, T. (1983). "A 64Kb full CMOS RAM with divided word line structure". 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. Vol. XXVI. pp. 58–59. doi:10.1109/ISSCC.1983.1156503. S2CID 34837669.
  58. Havemann, Robert H.; Eklund, R. E.; Tran, Hiep V.; Haken, R. A.; Scott, D. B.; Fung, P. K.; Ham, T. E.; Favreau, D. P.; Virkus, R. L. (December 1987). "An 0.8 μm 256K BiCMOS SRAM technology". 1987 International Electron Devices Meeting. pp. 841–843. doi:10.1109/IEDM.1987.191564. S2CID 40375699.
  59. Shahidi, Ghavam G.; Davari, Bijan; Dennard, Robert H.; Anderson, C. A.; Chappell, B. A.; et al. (December 1994). "A room temperature 0.1 μm CMOS on SOI". IEEE Transactions on Electron Devices. 41 (12): 2405–2412. Bibcode:1994ITED...41.2405S. doi:10.1109/16.337456. S2CID 108832941.
  60. ^ "Japanese Company Profiles" (PDF). Smithsonian Institution. 1996. Retrieved 27 June 2019.
  61. ^ "History: 1990s". SK Hynix. Archived from the original on 5 February 2021. Retrieved 6 July 2019.
  62. "Intel: 35 Years of Innovation (1968–2003)" (PDF). Intel. 2003. Retrieved 26 June 2019.
  63. The DRAM memory of Robert Dennard history-computer.com
  64. "Manufacturers in Japan enter the DRAM market and integration densities are improved" (PDF). Semiconductor History Museum of Japan. Retrieved 27 June 2019.
  65. ^ Gealow, Jeffrey Carl (10 August 1990). "Impact of Processing Technology on DRAM Sense Amplifier Design" (PDF). Massachusetts Institute of Technology. pp. 149–166. Retrieved 25 June 2019 – via CORE.
  66. "Silicon Gate MOS 2107A". Intel. Retrieved 27 June 2019.
  67. "One of the Most Successful 16K Dynamic RAMs: The 4116". National Museum of American History. Smithsonian Institution. Archived from the original on 2023-05-31. Retrieved 20 June 2019.
  68. Memory Data Book And Designers Guide (PDF). Mostek. March 1979. pp. 9 & 183.
  69. "The Cutting Edge of IC Technology: The First 294,912-Bit (288K) Dynamic RAM". National Museum of American History. Smithsonian Institution. Retrieved 20 June 2019.
  70. "Computer History for 1984". Computer Hope. Retrieved 25 June 2019.
  71. "Japanese Technical Abstracts". Japanese Technical Abstracts. 2 (3–4). University Microfilms: 161. 1987. The announcement of 1M DRAM in 1984 began the era of megabytes.
  72. ^ Robinson, Arthur L. (11 May 1984). "Experimental Memory Chips Reach 1 Megabit: As they become larger, memories become an increasingly important part of the integrated circuit business, technologically and economically". Science. 224 (4649): 590–592. doi:10.1126/science.224.4649.590. ISSN 0036-8075. PMID 17838349.
  73. MOS Memory Data Book (PDF). Texas Instruments. 1984. pp. 4–15. Retrieved 21 June 2019.
  74. "Famous Graphics Chips: TI TMS34010 and VRAM". IEEE Computer Society. 10 January 2019. Retrieved 29 June 2019.
  75. "μPD41264 256K Dual Port Graphics Buffer" (PDF). NEC Electronics. Retrieved 21 June 2019.
  76. "Sense amplifier circuit for switching plural inputs at low power". Google Patents. Retrieved 21 June 2019.
  77. "Fine CMOS techniques create 1M VSRAM". Japanese Technical Abstracts. 2 (3–4). University Microfilms: 161. 1987.
  78. Hanafi, Hussein I.; Lu, Nicky C. C.; Chao, H. H.; Hwang, Wei; Henkels, W. H.; Rajeevakumar, T. V.; Terman, L. M.; Franch, Robert L. (October 1988). "A 20-ns 128-kbit*4 high speed DRAM with 330-Mbit/s data rate". IEEE Journal of Solid-State Circuits. 23 (5): 1140–1149. Bibcode:1988IJSSC..23.1140L. doi:10.1109/4.5936.
  79. Breaking the gigabit barrier, DRAMs at ISSCC portend major system-design impact. (dynamic random access memory; International Solid-State Circuits Conference; Hitachi Ltd. and NEC Corp. research and development), January 9, 1995
  80. Scott, J.F. (2003). "Nano-Ferroelectrics". In Tsakalakos, Thomas; Ovid'ko, Ilya A.; Vasudevan, Asuri K. (eds.). Nanostructures: Synthesis, Functional Properties and Application. Springer Science & Business Media. pp. 584–600 (597). ISBN 9789400710191.
  81. "Toshiba's new 32 Mb Pseudo-SRAM is no fake". The Engineer. 24 June 2001. Archived from the original on 29 June 2019. Retrieved 29 June 2019.
  82. "A Study of the DRAM industry" (PDF). MIT. 8 June 2010. Retrieved 29 June 2019.
  83. ^ Here, K, M, G, or T refer to the binary prefixes based on powers of 1024.
  84. "KM48SL2000-7 Datasheet". Samsung. August 1992. Retrieved 19 June 2019.
  85. ^ "MSM5718C50/MD5764802" (PDF). Oki Semiconductor. February 1999. Archived (PDF) from the original on 2019-06-21. Retrieved 21 June 2019.
  86. "Ultra 64 Tech Specs". Next Generation. No. 14. Imagine Media. February 1996. p. 40.
  87. ^ "History: 1990s". az5miao. Retrieved 4 April 2022.
  88. "Direct RDRAM" (PDF). Rambus. 12 March 1998. Archived (PDF) from the original on 2019-06-21. Retrieved 21 June 2019.
  89. ^ "Samsung Electronics Comes Out with Super-Fast 16M DDR SGRAMs". Samsung Electronics. Samsung. 17 September 1998. Retrieved 23 June 2019.
  90. ^ "Samsung Electronics Develops First 128Mb SDRAM with DDR/SDR Manufacturing Option". Samsung Electronics. Samsung. 10 February 1999. Retrieved 23 June 2019.
  91. ^ "Samsung Demonstrates World's First DDR 3 Memory Prototype". Phys.org. 17 February 2005. Retrieved 23 June 2019.
  92. ^ "History". Samsung Electronics. Samsung. Retrieved 19 June 2019.
  93. ^ "EMOTION ENGINE AND GRAPHICS SYNTHESIZER USED IN THE CORE OF PLAYSTATION BECOME ONE CHIP" (PDF). Sony. April 21, 2003. Archived (PDF) from the original on 2017-02-27. Retrieved 26 June 2019.
  94. ^ "History: 2000s". az5miao. Retrieved 4 April 2022.
  95. "Samsung Develops the Industry's Fastest DDR3 SRAM for High Performance EDP and Network Applications". Samsung Semiconductor. Samsung. 29 January 2003. Retrieved 25 June 2019.
  96. "Elpida ships 2GB DDR2 modules". The Inquirer. 4 November 2003. Archived from the original on July 10, 2019. Retrieved 25 June 2019.
  97. "Samsung Shows Industry's First 2-Gigabit DDR2 SDRAM". Samsung Semiconductor. Samsung. 20 September 2004. Retrieved 25 June 2019.
  98. "ソニー、65nm対応の半導体設備を導入。3年間で2,000億円の投資". pc.watch.impress.co.jp. Archived from the original on 2016-08-13.
  99. ATI engineers by way of Beyond 3D's Dave Baumann
  100. "Our Proud Heritage from 2000 to 2009". Samsung Semiconductor. Samsung. Retrieved 25 June 2019.
  101. "Samsung 50nm 2GB DDR3 chips are industry's smallest". SlashGear. 29 September 2008. Retrieved 25 June 2019.
  102. ^ "History: 2010s". az5miao. Retrieved 4 April 2022.
  103. "Our Proud Heritage from 2010 to Now". Samsung Semiconductor. Samsung. Retrieved 25 June 2019.
  104. "Samsung Electronics Announces Industry's First 8Gb LPDDR5 DRAM for 5G and AI-powered Mobile Applications". Samsung. July 17, 2018. Retrieved 8 July 2019.
  105. "Samsung Unleashes a Roomy DDR4 256GB RAM". Tom's Hardware. 6 September 2018. Archived from the original on June 21, 2019. Retrieved 4 April 2022.
  106. HM5283206 Datasheet. Hitachi. 11 November 1994. Retrieved 10 July 2019.
  107. "Hitachi HM5283206FP10 8Mbit SGRAM" (PDF). Smithsonian Institution. Archived (PDF) from the original on 2003-07-16. Retrieved 10 July 2019.
  108. μPD481850 Datasheet. NEC. 6 December 1994. Retrieved 10 July 2019.
  109. NEC Application Specific Memory. NEC. Fall 1995. p. 359. Retrieved 21 June 2019.
  110. UPD4811650 Datasheet. NEC. December 1997. Retrieved 10 July 2019.
  111. Takeuchi, Kei (1998). "16M-BIT SYNCHRONOUS GRAPHICS RAM: μPD4811650". NEC Device Technology International (48). Retrieved 10 July 2019.
  112. "Samsung Announces the World's First 222 MHz 32Mbit SGRAM for 3D Graphics and Networking Applications". Samsung Semiconductor. Samsung. 12 July 1999. Retrieved 10 July 2019.
  113. ^ "Samsung Electronics Announces JEDEC-Compliant 256Mb GDDR2 for 3D Graphics". Samsung Electronics. Samsung. 28 August 2003. Retrieved 26 June 2019.
  114. "K4D553238F Datasheet". Samsung Electronics. March 2005. Retrieved 10 July 2019.
  115. "Samsung Electronics Develops Industry's First Ultra-Fast GDDR4 Graphics DRAM". Samsung Semiconductor. Samsung. October 26, 2005. Retrieved 8 July 2019.
  116. "K4W1G1646G-BC08 Datasheet" (PDF). Samsung Electronics. November 2010. Archived (PDF) from the original on 2022-01-24. Retrieved 10 July 2019.
  117. Shilov, Anton (March 29, 2016). "Micron Begins to Sample GDDR5X Memory, Unveils Specs of Chips". AnandTech. Retrieved 16 July 2019.
  118. ^ Shilov, Anton (July 19, 2017). "Samsung Increases Production Volumes of 8 GB HBM2 Chips Due to Growing Demand". AnandTech. Retrieved 29 June 2019.
  119. "HBM". Samsung Semiconductor. Samsung. Retrieved 16 July 2019.
  120. "Samsung Electronics Starts Producing Industry's First 16-Gigabit GDDR6 for Advanced Graphics Systems". Samsung. January 18, 2018. Retrieved 15 July 2019.
  121. Killian, Zak (18 January 2018). "Samsung fires up its foundries for mass production of GDDR6 memory". Tech Report. Retrieved 18 January 2018.
  122. "Samsung Begins Producing The Fastest GDDR6 Memory In The World". Wccftech. 18 January 2018. Retrieved 16 July 2019.

External links

  • Media related to RAM at Wikimedia Commons
Basic computer components
Input devices
Pointing devices
Other
Output devices
Removable
data storage
Computer case
Ports
Current
Obsolete
Related
Categories:
Random-access memory: Difference between revisions Add topic